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Microchip PIC16C5x instruction set summary


with Ubicom SX extensions

This is the "12-bit core" instruction set.

Mnemonic,      Description                       Cycles     Status    12-Bit Opcode	      
   Operands                                      /Turbo     Affected  MSB         LSB     Notes
===============================================================================================
ADDWF   f,d    Add W and f                         1        C,DC,Z    0001  11df  ffff    1,2,4
ANDWF   f,d    AND W with f                        1        Z         0001  01df  ffff    2,4
CLRF    f      Clear f                             1        Z         0000  011f  ffff    4
CLRW    -      Clear W                             1        Z         0000  0100  0000     
COMF    f,d    Complement f                        1        Z         0010  01df  ffff     
DECF    f,d    Decrement f                         1        Z         0000  11df  ffff    2,4
DECFSZ  f,d    Decrement f, Skip if 0              1(2)     None      0010  11df  ffff    2,4
INCF    f,d    Increment f                         1        Z         0010  10df  ffff    2,4
INCFSZ  f,d    Increment f, Skip if 0              1(2)     None      0011  11df  ffff    2,4
IORWF   f,d    Inclusive OR W with f               1        Z         0001  00df  ffff    2,4
MOVF    f,d    Move f                              1        Z         0010  00df  ffff    2,4
MOVWF   f      Move W to f                         1        None      0000  001f  ffff    1,4
NOP     -      No Operation                        1        None      0000  0000  0000        
RLF     f,d    Rotate left f through Carry         1        C         0011  01df  ffff    2,4
RRF     f,d    Rotate right f through Carry        1        C         0011  00df  ffff    2,4
SUBWF   f,d    Subtract W from f (Different on SX) 1        C,DC,Z    0000  10df  ffff    1,2,4
SWAPF   f,d    Swap f                              1        None      0011  10df  ffff    2,4
XORWF   f,d    Exclusive OR W with f               1        Z         0001  10df  ffff    2,4
-----------------------------------------------------------------------------------------------
Bit-oriented file register operations                       
-----------------------------------------------------------------------------------------------
BCF     f,b    Bit Clear f                         1        None      0100  bbbf  ffff    2,4
BSF     f,b    Bit Set f                           1        None      0101  bbbf  ffff    2,4
BTFSC   f,b    Bit Test f, Skip if Clear           1(2)     None      0110  bbbf  ffff        
BTFSS   f,b    Bit Test f, Skip if Set             1(2)     None      0111  bbbf  ffff        
-----------------------------------------------------------------------------------------------
Literal and control operations                              
-----------------------------------------------------------------------------------------------
ANDLW   k      AND Literal with W                  1        Z         1110  kkkk  kkkk     
CALL    k      Call subroutine                     2/3      None      1001  kkkk  kkkk    1
CLRWDT  k      Clear Watchdog Timer                1        TO,PD     0000  0000  0100         
GOTO    k      Unconditional branch                2/3      None      101k  kkkk  kkkk        
IORLW   k      Inclusive OR Literal with W         1        Z         1101  kkkk  kkkk     
MOVLW   k      Move Literal to W                   1        None      1100  kkkk  kkkk        
OPTION  k      Load OPTION register with W         1        None      0000  0000  0010        
RETURN         Return (from subroutine)            2/3      None      0000  0000  1100        
RETLW   k      Return (fr subr) move Literal to W  2/3      None      1000  kkkk  kkkk        
SLEEP   -      Power down WDT=0, Pre=0, TO=1, PD=0 1        TO,PD     0000  0000  0011         
TRIS    f      Move W into Port Control Register   1        None      0000  0000  0fff    3
XORLW   k      Exclusive OR Literal to W           1        Z         1111  kkkk  kkkk     

-----------------------------------------------------------------------------------------------
Scenix/Ubicom extensions                                           
-----------------------------------------------------------------------------------------------
BANK    n      Write n into FSR7, FSR6 and FSR5    1        None      0000  0001  1nnn    5  
IREAD   -      Read word at (MODE:W) into MODE:W   1/4      None      0000  0100  0001        
MODE    n      Write n into MODE register          1        None      0000  0101  nnnn        
MOVMW   -      Read MODE bits into W. (Hi nib=0)   1        None      0000  0100  0010        
MOVWM   -      Write W into MODE register          1        None      0000  0100  0011        
PAGE    n      Write n into PA2, PA1 and PA0       1        PA2/1/0   0000  0001  0nnn    5
RET     -      Return without affecting W          2/3      None      0000  0000  1100        
RETI    -      Ret fr int. Pop PC, W, STATUS, FSR  2/3  All but TO,PD 0000  0000  1110         
RETIW   -      RETI and add W to RTCC              2/3  All but TO,PD 0000  0000  1111         
RETP    -      Ret, W unchanged, Pop PA2,PA1,PA0   2/3      PA2/1/0   0000  0000  1101         
-----------------------------------------------------------------------------------------------
MPLAB Macros
-----------------------------------------------------------------------------------------------


Note:

by Loren Blaney via Richard Ottosen

Also:

Archive:

See also:


Comments:

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This is understandable that money makes people free. But how to act when one does not have cash? The only one way is to receive the credit loans and car loan.
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