movlw variable_name movwf FSR
Using < movlw > is the key.
DS80058B PIC18CXX2 Rev. B Silicon Errata Sheet "Using the LFSR instruction to load a value into the specified FSR register may also corrupt a RAM location. Do not use the LFSR instruction."
Bob Ammerman says:
Another use or two or three of FSR:
To pass an argument by reference to a subroutine so that one subroutine can be used with varying data. I use this for code that manages debounce state on buttons.
To allow the same code to be used to hit two different I/O ports.
And my favorite:
I sometimes use 'open-collector' type communication channels. To implement these one would typically set the port register bit to zero, and then use the TRIS register bit to control the output (zero or float).
In order to avoid bank switch inside tight loops, I'll do this:movlw TRISB movwf FSR
now I can:bcf INDF,n or bsf INDF,n
to output my bits without having to bank switch.
Andrew Warren says:
Remember that in the 16C5x processors, the unused upper bits of the FSR always read as "1".
On the 16C54, for instance, the upper three bits are set that way, which means that the FSR will always contain an address in the range 0xE0-0xFF.
Therefore, when you test the FSR for equality to some number, you must either AND the FSR with 00011111 or OR the number with 11100000 before the comparison.
That's a drag, but if you're just using the FSR to clear RAM, the "111" in the upper three bit-positions actually helps:MOVLW 5 ;Start clearing RAM at register 0x05. MOVWF FSR LOOP: CLRF INDF INCFSZ FSR ;Stop clearing RAM at register 0x1F. GOTO LOOP
The "INCFSZ" will get us out of the loop after we've cleared register 0x1F, even though our code doesn't explicitly compare FSR to 0x1F anywhere. It works like this:The FSR starts at 11100101 (we write 0x05 to it, but the high 3 bits are always set), then we iterate through the loop until the FSR holds 11111111 (0x1F with the high 3 bits set).
At that point, our INCFSZ reads the FSR (11111111) and increments it to 00000000. That triggers the "skip" part of the INCFSZ, even though FSR will hold 11100000, not 00000000, after we exit the loop.
One note about PICs with > 256 bytes of RAM is that you need to take note of the STATUS,IRP bit. This is the 9th FSR bit so you can access RAM above 255. STATUS,RP0 & RP1 are not used with indirect addressing.
Moving blocks of data in memory
|file: /Techref/microchip/fsr.htm, 4KB, , updated: 2014/10/30 10:20, local time: 2017/2/25 08:28,
|©2017 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://www.piclist.com/techref/microchip/fsr.htm"> PIC Microcontoller Memory Method </A>
|Did you find what you needed?|
PICList 2017 contributors:
o List host: MIT, Site host massmind.org, Top posters @20170225 IVP, RussellMc, Van Horn, David, Neil, James Cameron, Sean Breheny, alan.b.pearce, Bob Blick, Denny Esterline, David Duffy (AVD),
* Page Editors: James Newton, David Cary, and YOU!
* Roman Black of Black Robotics donates from sales of Linistep stepper controller kits.
* Ashley Roll of Digital Nemesis donates from sales of RCL-1 RS232 to TTL converters.
* Monthly Subscribers: Gregg Rew. on-going support is MOST appreciated!
* Contributors: Richard Seriani, Sr.
Welcome to www.piclist.com!