The SX 48/52 was (is) a monster chip (4K code space, 262 registers, 4 to 5 - 8 bit IO ports, 2 16 bit timers!) but despite all that it went mostly unused among experimental users. Why? I don't think it was the chip cost... they have been available for $7 to $12 dollars in single quantities.
Now Ubicom is releaseing the IP 2022. If you thought the 48/52 was killer, check out these stats:
What sort of adapter can we make? What was available for the 52 and what can we learn from the mistakes? Can we avoid missing out this time?
This image is an example of the sort of adapter I'm thinking of. Click on it to see it up close. There is a 48 pin PQFP pad set inside a 52 pin PQFP pad set and if you look outside that, you can see the three rows of pads and holes on each side for the test socket. The four large holes at the corners are the alignment holes and mounts for the test socket. The IO pins are arrayed around the edge and there are pads for Power, Master clear and RTCC next to the header for the ISP in the upper left.
This layout was done using Express PCBs propritary layout editor before I knew any better (I'm much more software than hardware) and the layout parameters were restricted when they upgraded the software, makeing this layout impossible for them to make due to its complexity. Perhaps it's overly complex for anyone to make!
What's wrong with this design?
This is an adapter (pn: 160-8404-07) I purchased from www.adapters.com some time ago. A great site if you really, really need quantity one of some wierd adapter that no one else can get.
What's wrong with this design?
Mouser stock numbers 571-41031480 .230 .120 571-41029780 .318 .110
|3||A3||Special IO or Negative Supply|
|4||PWR||Unregulated DC (VPP) 7.5 to 18 VDC|
|5||CI/A4||Clock In/Special IO Note 1|
|6||CO/A5||Clock Out/Special IO Note 1|
|7||VDD||+5V In or Out +/- 5%|
|8||RES||Reset In or Out. Active Low.|
|10||SCL||I2C Clock or IO|
|11||SDA||I2C Data or IO|
|12||SI||Serial In or IO|
|13||SO||Serial Out or IO|
|15||D0||General Purpose IO|
|16||D1||General Purpose IO|
|17||D2||General Purpose IO|
|18||D3||General Purpose IO|
|19||D4||General Purpose IO|
|20||D5||IO/MOSI or SPI Master Out Slave In Note 2|
|21||D6||IO/MISO or SPI Master In Slave Out Note 2|
|22||D7||IO/SCK or SPI Clock Note 2|
|23||D8||General Purpose IO|
|24||D9||General Purpose IO|
|25||D10||General Purpose IO|
|26||D11||General Purpose IO|
|27||D12||General Purpose IO|
|28||D13||General Purpose IO|
|29||D14||General Purpose IO|
|30||D15||General Purpose IO|
Note 1 ***
We feel the most misused, abused, and never used pins are the clock lines. Should never have come out at all. The guru did make a mistake here. As we redesign boards, we will remove these tracks, but it could be years now of course before it filters through. Have added the alternative pin designations A4 and A5. Scenix Micros use the clock lines for programming, so these may need to be routed via the "A" lines or perhaps a programming header.
Note 2 ***
For SPI Operation, an additional I/O is required for the Chip Select of each SPI Device.
|file: /Techref/scenix/contest/4852adapt.htm, 13KB, , updated: 2005/8/26 14:35, local time: 2022/10/5 21:54,
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