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PIC/SX RAM Table Pulse Width Modulation

Dan Michaels says:

"Math-Averse, Stupid Guy's, Hi-Speed 8-Channel PWM"

Use a lookup table.

The uC can't do anything else when it's running, and you may get a fairly-long pause every time you change one of the 8 duty cycle values, since you have to reload or recalculate the entire table.

**BUT**

On a 20 Mhz PIC, you could get rock-steady 8-channel PWM at maybe 1-2 usec/step, or 1953-3906 Khz for 256 steps.

Or switching to a 50 Mhz Scenix SX18, you can get rock-steady *7* bit 8-channel PWM at 200 nsec/step, or 39,062 Khz - limited to 7 bits since SX RAM = 128 bytes.

; (send block to port B - 10 clocks/loop = 200 nsec).
send_block
        jmp     :L3       ; jump to re-start (initialization).

:lp1    nop               ; can insert code here for bailout.
        nop
        nop
:lp2    setb    FSR.4
        mov     w,IND
        mov     rb,w
        incsz   FSR
        jmp     :lp1      ; jmp takes 3 clocks on SX.

; (reload - re-entry takes exactly 10 clocks).
:L3     mov     w,#bufstart
        mov     FSR,w
        jmp     :lp2

[sorry to inject heretical scenix code into the PIC universe].

Better yet, you can easily spread the PWM energy evenly over the period, to minimize external circuitry hassles. Better yet - no need to jump into FPGA technology, if you aren't already there.

Also:

Questions:

See also:


file: /Techref/scenix/lib/io/osi1/pwm/rampwm.htm, 2KB, , updated: 2008/2/11 15:34, local time: 2019/2/18 03:52,
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