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Ubicom SX Embedded Controller Interupts

Timer interrupt and External and Wakeup interrupts

The device supports both internal and external maskable interrupts. The internal interrupt is generated as a result of the RTCC rolling over from 0FFh to 00h. This interrupt source has an associated enable bit located in the OPTION register. There is no pending flag associated with this interrupt.

Port B provide the source for eight external software selectable, edge sensitive interrupts, when the device is not in the SLEEP mode. These interrupt sources share logic with the Multi-Input Wakeup circuitry. The WKEN_B register allows interrupt from Port B to be individually enabled or The WKED_B selects the transition edge to be either positive or negative. The WKEN_B and WKED_B registers are cleared upon reset. The WKPND_B register serves as the external interrupt pending register. Pulses as short as 6 nano seconds will reliably trigger an interrupt.


External and Wakeup interrupts


The power down mode is entered through the execution of the SLEEP instruction while the SLEEP mode is enabled.

In SLEEP mode, only the Watchdog Timer (WDT) is active. If the Watchdog Timer is enabled, upon execution of the SLEEP instruction, the Watchdog Timer is cleared, the TO bit is set in the STATUS register, and the PD bit is cleared in the STATUS register.

There are three different ways to exit from the low power sleep mode: a timer overflow signal from the Watchdog Timer (WDT), a valid transition on any of the Multi-Input Wakeup pins (Port B pins), or through an external reset input on the MCLR pin.

To achieve the lowest possible power consumption, the Watchdog Timer should be disabled and the device should exit the SLEEP mode through the MIWU pins or an external reset.

7.1 Multi-Input Wakeup

Multi-Input Wakeup is one way of causing the device to exit the power down mode. Port B is used to support this feature. The WKEN_B register (Wakeup Enable Regis-ter) allows any Port B pin or combination of pins to cause the wakeup. Setting a bit in the WKEN_B register enables the wakeup on the corresponding Port B pin. If multi-input wakeup is selected to cause a wakeup, the trigger condition on the selected pin can be either rising edge (low to high) or falling edge (high to low). The WKED_B register (Wakeup Edge Select) selects the desired transition edge. Setting a bit in the WKED_B register selects the falling edge on the corresponding Port B. Resetting the bit selects the rising edge. The WKEN_B and WKED_B registers are cleared upon reset.

Once a valid transition occurs on the selected pin, the WKPND_B register (Wakeup Pending Register) latches the transition in the corresponding bit position. A logic ‘1’ indicates the occurrence of the selected trigger edge on the corresponding Port B pin.

Note: if you are waiting for a high to low, or a low to high, either one, when it happens, you get a 1 in that bit position in WKPND_B.

Upon exiting the power down mode, the Multi-Input Wakeup logic causes program counter to branch to the maximum program memory address (same as reset). Figure 7-1 shows the Multi-Input Wakeup block diagram.

The following problem was reported on early version chips:

>>We are experiencing a problem when using the port B interrupt on an 18 pin 9818 date device. If another interrupt is received before the first code has cleared and returned, the interrupt system becomes inoperative however non interrupt code keeps running. Is this a known bug or is there something we need to do within or when exiting the interrupt code to stop this happening.>>

All current parts in distribution have this bug. All new revisions of the core, including SX48/52 include an extra entry in the state table to go back to the interrupt vector if there is anything in the pending register on return from the interrupt service routine. The current (and all older) parts will not properly return to the interrupt vector if an interrupt came in during the ISR. There are software fixes that seem to work in the code I've tried, and they are as follows:

1. Disable, and then re-enable the RTCC interrupt before returning from the ISR. This resets the internal interrupt, and if currently servicing an external interrupt, an internal interrupt edge can be detected.

2. Clear, and then reload the pending register with its original value prior to the return from the ISR. This resets the external interrupts, so a new edge can be detected. Example code:

mov m,#$09 ;Set up to read wake up pending register
clr w
mov !rb,w ;Swap w with WKPND_B register
mov !rb,w ;Swap w with WKPND_B register again to restore original value

If only internal interrupts are being used, only fix 1 needs to be applied. If only external interrupts are being used, only fix 2 needs to be applied.

Stephen Holland says:

If multiple sources of port B interrupt are enabled, always ensure that only the bits for the interrupts that have been serviced are cleared. The SX state machine will check the pending register upon return from the ISR to see if there are any bits set, and if so, will re-enter the ISR. This was a bug in older SX devices (with the old datecodes), where the external interrupts had to be disabled and then reenabled before the RETI or RETIW. Otherwise, any pending bits that were set would never trigger again, as the edge condition would be forever lost. {and since the only way to look at the bits is by swaping them out, you would have to swap them back to avoid clearing the all, and if a new int happens to occur between the swaps, you will miss one again.}

Loren Blaney and Richard Ottosen say:

WKPND should be cleared before enabling WKEN interrupts, otherwise a spurious interrupt will occur.

The interrupt service routine must clear WKPND to enable additional interrupts on the MIWU pin.

Alexey Vladimirov [avlad at] says:

Typical interrupt service routine contain the following code:
  mov m,#$09 ;Set up to read wake up pending register 
  clr w 
  mov !rb,w ;Read WKPND_B register content and clear it after that

Each SX instruction in turbo mode executed in a 4-stage pipeline, consisting of the following steps: fetch instruction, decode opcode, execute opcode, write result.

In the example mov !rb, w instruction at the second step simultaneously with instruction decode also read WKPND_B register and at the fourth step clear WKPND_B register.

If another external interrupt on different portB pin occurs exactly at this time (at the 2,3,4 steps of the mov !rb, w execution), SX will loose this interrupt (as the WKPND_B register cleared and, therefore, pending bit for this interrupt also cleared without interrupt processing).

It mean, that it is not possible to use 2 or more asynchronous external interrupts on the SX without loosing some interrupts.

This problem related to all current (as of Jan 2001) SX revisions.

[To work around this, check the pins by reading the actual port value after the first interrupt.] If you will use polling instead of interrupts - all will works OK. You can also use one external interrupt and poll other pins. However, if you have two asynchronous signals and you need interrupt on both (bridge application, for example), the only possible workaround we found - add some external glue logic (triggers for each interrupt with separate reset from SX port, as in any typical interrupt controller, like 8259) or change from interrupts to polling.





See also:

file: /Techref/scenix/sxints.htm, 23KB, , updated: 2007/11/16 14:03, local time: 2018/8/17 06:56,

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