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SX Watchdog Timer

Stephen C. Holland Says:

Wherever you put the CLR !WDT instruction in your main loop, you need to make sure you can get there before the watchdog timer will overflow.

The documentation of the watchdog in the Ubicom/Scenix datasheets is really weak. Basically, the watchdog runs from it's own internal oscillator which runs at ~14KHz, or a period of 714us. Ath this rate, the 8-bit counter counts from 0x00 to 0xFF in 18ms. This amount of time is the default watchdog timeout period. The watchdog timeout can be increased by using the 8-bit prescaler register, as long as you are not already using it for the RTCC. You can assign the prescaler to the RTCC or watchdog by controlling the PSA bit in the OPTION register. The prescaler is then configured with the PS[2:0] bits in the OPTION register.The watchdog can also run in power down mode. In your reset software, you can then look at the TO bit to see if a watchdog timeout occured. You may want to have some different initialization if the watchdog occurs.

I have attached some code I wrote awhile back to check for all forms of reset in the reset vector. It's a little old, and may contain some errors (it was written when an older version of SASM was around) With this, you can know if you are in the reset vector because of power up or MCLR, watchdog timeout, or MIWU (from sleep mode). You could extend the power-up/MCLR code to actually test for the presence of some software-initialized RAM locations to tell between an MCLR and power-up condition. The reason for this is that the RAM comes up at unkown values on power-up, but would remain the same as whatever they were last set to on an MCLR. This is a similiar approach used in your car radio so that it keeps it's presets after it powers up.

+

Code:

See also:


file: /Techref/scenix/watchdog.htm, 30KB, , updated: 2003/1/4 23:23, local time: 2017/12/17 05:38, owner: SCH-NSC-LA7,
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