There does not appear to be any documentation of the minimum pulse width that will reliably trigger an interupt on the SX devices.
Peter Van der Zee says:
As this issue is also interesting to me, I decided to do some tests, and here are the results.
Operating at 5 volts and room temperature, turbo mode, and triggering the pulse into port B.0, the threshold of pulse detection was 5 nano seconds (as short as my pulse generator will go) with about 80% success. Stretching this to 6 nano seconds or longer brought the detection to 100%.
It worked identically for detecting rising and falling edges, and it captured equally well at 50 Mhz using SX-Key's clock and 4Mhz internal clock.
At 50 Mhz the minimum delay time in entering interrupt was 100 nano seconds, equal to 5 instructions, and the maximum delay was 120 nano seconds, the difference of course being the asynchronicity between the pulse generator and the processor clock.
At 4 Mhz the minimum delay time in entering interrupt was 1000 nano seconds, equal to 4 instructions, and the maximum delay was 1250 nano seconds.
It would appear that there is some 20 nano seconds of transit delay which of course is not noticable at the slower speed, but shows up as the equivalent time of one instruction at 50 Mhz.
The delay testing was done by triggering one channel of my oscilloscope on the pulse edge, and observing an RB.7 bit-set flag as the first instruction in the interrupt on another channel. The scope bandwidth was set to 500 Mhz.
Because the observable bit-set (read-modify-write) occurs near the end on a processor cycle, the duration of the bit-set instruction (20 nano seconds for the 50 Mhz case) was subtracted from the observed time, giving the net results indicated above. In other words, the actual time observed on the scope was one instruction longer time than the true time to enter interrupt; the final instruction cycle does not count in determining the number of cycles to get from the pulse edge into interrupt.
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