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Intel 80486 CPU


Ref: PC Magazine

Intel's 80486 uses a cache scheme called four-way set associative. In this
design, the internal 8k of cache (governed by an internal controller) is
divided into four 2k blocks. Each block contains 32 sets of 4 lines, and each
line is 16 bytes wide. Each set in the cache holds data for a given location in
memory. When the 80486 needs to access memory, the cache looks at the set
assigned to the appropriate memory location to determine whether the data has
indeed been cached.

Intel claims that its 8k internal cache using set-associative techniques is as
effective as 32k of cache using the direct mapped method common with 80386DX
systems. For the 8k internal cache, the hit rate is estimated at 90 percent.
Nine times out of ten, when a memory read is to be made, the data will be found
in cache.


Picture of the die

Task Save Segment

History
The 80486 offered little in the way of architectural enhancements over its 80386 predecessor. The most significant enhancement of the 486 family was the integration of the 80387-math coprocessor into the 80486-core logic. Now, all software that requires the math coprocessor could run on the 80486 without any expensive hardware upgrades.
Like the 80386 SX, Intel decided to introduce the 80486 SX as a cost-reduced 80486 DX. Unfortunately, Intel chose to ensure that these processors were neither pin-compatible, nor 100% software compatible with each other. Unlike the 80386 SX, the 80486 SX enjoyed the full data bus and address bus of its DX counterpart. Instead, Intel removed the math coprocessor, thereby rendering the 80486 SX somewhat software incompatible with its DX counterpart. To further complicate matters, Intel introduced the 80487 SX -- the "math coprocessor" to the 80486 SX. Intel convinced vendors to include a new socket on the motherboard that could accommodate the 80486 SX and 80487 SX as an expensive hardware upgrade option. Unbeknownst to the consumer, the 80486 SX was an 80486 DX with a non-functional math unit (though later versions of the chip actually removed the math unit). The 80487 SX was a full 80486 DX with a couple of pins relocated on the package -- to prevent consumers from using the cheaper 80486 DX as an upgrade option. In this regard, Intel created a marketing deception. Intel marketed the 80487 SX as a math coprocessor to the 80486 SX. In reality, the 80487 SX electronically disabled the 80486 SX when installed, thereby relegating this chip to the status of an expensive space heater. Sadly, the consumer never knew or even suspected Intel of playing such manipulative games.
Also like the 80386, the Intel began to diversify their 80486 offerings. Low-power versions of the chip were introduced. The 80486 SL was introduced along with the 80386 SL as an integrated, low-power chip for notebook applications. The 80486 DX2 and DX4 were introduced, which doubled and tripled the core clock frequency. Power-saving features from the SL were introduced in later versions of the DX4. Finally, after Intel introduced the Pentium chip, they produced a version of the Pentium that was pin-compatible with the 80486. They called this chip an "overdrive" processor.
Likewise, AMD and Cyrix continued to pursue their own 486-compatible chip solutions. AMD introduced many Am486 variants. Cyrix continued their nomenclature of calling an 80486-compatible chip, the Cyrix 5x86. TI continued to manufacture Cyrix chips, and eventually started their own in-house microprocessor design (though the effort eventually failed). UMC entered the CPU market, but later withdrew because of patent infringement problems. IBM began manufacturing for Cyrix, and still pursuing their own microprocessor designs (the Blue Lightning series).

See also:


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