please dont rip this site 
     Task State Segment (TSS) for a 486

31                     16 15         <- bits     0
+------------------------+------------------------+
|  0000 0000 0000 0000   |       BACK LINK        |   0 (TSS base)
|                      ESP0                       |   4
|  0000 0000 0000 0000   |          SS0           |   8
|                      ESP1                       |   C
|  0000 0000 0000 0000   |          SS1           |  10
|                      ESP2                       |  14
|  0000 0000 0000 0000   |          SS2           |  18
|                       CR3                       |  1C
|                       EIP                       |  20
|                     EFLAGS                      |  24
|                       EAX                       |  28
|                       ECX                       |  2C
|                       EDX                       |  30
|                       EBX                       |  34
|                       ESP                       |  38
|                       EBP                       |  3C
|                       ESI                       |  40
|                       EDI                       |  44
|  0000 0000 0000 0000   |            ES          |  48
|  0000 0000 0000 0000   |            CS          |  4C
|  0000 0000 0000 0000   |            SS          |  50
|  0000 0000 0000 0000   |            DS          |  54
|  0000 0000 0000 0000   |            FS          |  58
|  0000 0000 0000 0000   |            GS          |  5C
|  0000 0000 0000 0000   |           LDT          |  60
|  BIT_MAP_OFFSET(15:0)  |  0000 0000 0000 000  |T|  64   T= debug trap bit
+------------------------+------------------------+
|  Available                                      |
|               SYSTEM STATUS, ETC.               |
\\                                               \\
\\                      ...                      \\
|                                                 |
+------------------------+------------------------+
|31       24|23        16|15         8|7         0|  BIT_MAP_OFFSET
|63       56|55        48|47        40|39       32|  BIT_MAP_OFFSET + 4
|95       88|87        80|79        72|71       64|  BIT_MAP_OFFSET + 8
\\                      ...                      \\  etc.
\\                                               \\
|65471      |            |            |      65440|  BIT_MAP_OFFSET + 1FF4
|65503      |            |            |      65472|  BIT_MAP_OFFSET + 1FF8
|65535      |            |            |      65504|  BIT_MAP_OFFSET + 1FFC
+-----------+------------+------------|    "FFh"  |  BIT_MAP_OFFSET + 2000
                                      +-----------+

Notes:
1.  ESP0-3, and SS0-3  are the stacks for CPL 0,1 and 2
2.  BIT_MAP_OFFSET must be <= DFFFh
3.  The I/O Permission bitmap uses one bit per I/O port address and
    may be truncated using the TSS limit in the TSS Register.
4.  The backlink is a pointer to the previous TSS.  It is used when
    a CALL or INT instruction causes a task switch.
file: /techref/intel/80486/tss.htm, 3KB, , updated: 2000/2/16 13:35, local time: 2010/3/19 14:42,
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