Source code and Explanation for peripheral circuit for Digital Clock

Source code and Explanation
for peripheral circuit for Digital Clock

--**********************************************************************************
--*                                                                                *
--*                           Digital Clock peripheral logic                       *
--*                                                         Device : XC9536-PC44   *
--*                                                         Author : Seiichi Inoue *
--**********************************************************************************
library IEEE;                                         -- Library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock2 is
    Port ( S,R : in std_logic_vector(1 downto 0);     -- SR-FF INPUT
           Q : out std_logic_vector(1 downto 0);      -- SR-FF OUTPUT
           CLK_10M : in std_logic;                    -- 1/200000 counter INPUT
           CLK_50 : out std_logic;                    -- 1/200000 counter OUTPUT
           A,B,C : in std_logic;                      -- 3-8 Decoder INPUT
           DEC : out std_logic_vector(7 downto 0));   -- 3-8 Decoder OUTPUT
  attribute pin_assign : string;                      -- Pin assign
  attribute pin_assign of S : signal is "6,2";
  attribute pin_assign of R : signal is "4,44";
  attribute pin_assign of Q : signal is "42,40";
  attribute pin_assign of CLK_10M : signal is "7";
  attribute pin_assign of CLK_50 : signal is "39";
  attribute pin_assign of A : signal is "37";
  attribute pin_assign of B : signal is "35";
  attribute pin_assign of C : signal is "33";
  attribute pin_assign of DEC : signal is "27,25,28,26,22,20,18,24";
end clock2;

architecture clock2_arch of clock2 is
  signal SI,RI,QI,QRI : std_logic_vector(1 downto 0); -- SR-FF signals
  signal Q100K : std_logic_vector(16 downto 0);       -- 1/100000 counter
  signal QCLK : std_logic_vector(0 downto 0);         -- 1/2 counter
  signal IN_DATA : std_logic_vector(2 downto 0);      -- 3-8 Decoder signals

begin
-- ** SR-FF **
  Q <= QI;                                            -- Set OUTPUT
  QI <= S nand SI;                                    -- Make NAND
  QRI <= R nand RI;                                   -- Make NAND
  SI <= QRI;                                          -- Connect QRI and SI
  RI <= QI;                                           -- Connect QI and RI

-- ** 1/200000 counter **
  CLK_50 <= QCLK(0);                                  -- Set OUTPUT
  process( CLK_10M ) begin
    if CLK_10M='1' and CLK_10M'event then             -- Clock rising edge ?
      if Q100K=99999 then                             -- Count = 100000 ?
         Q100K <= "00000000000000000";                -- YES. Clear counter
         QCLK <= QCLK + '1';                          -- Set 1/200000 counter
      else                                            -- No.
         Q100K <= Q100K + '1';                        -- Count-up
      end if;
    end if;
  end process;

-- ** 3-8 Decoder **
  IN_DATA <= C & B & A;                               -- Binding vector
  process( IN_DATA ) begin
    case IN_DATA is                                   -- Decode with input data
      when "000" => DEC <= "11111110";
      when "001" => DEC <= "11111101";
      when "010" => DEC <= "11111011";
      when "011" => DEC <= "11110111";
      when "100" => DEC <= "11101111";
      when "101" => DEC <= "11011111";
      when "110" => DEC <= "10111111";
      when "111" => DEC <= "01111111";
      when others => DEC <= "XXXXXXXX";               -- Illegal condition
    end case;
  end process;

end clock2_arch;

--**********************************************************************************
--*                       end of Digital Clock peripheral logic                    *
--**********************************************************************************

Explanation

Line #	Comment
007 -010	The std_logic library is specified. When using WebPACK 3.1WP1.x, these libraries are automatically designated.
013 -018	The ports of the input/output are specified. It is designated by the vector because it makes two sets of SR-FF. The output of the 3-8 decoder is designated by the vector to make a set with eight bits.
019 -028	The pins of the input/output are specified. In case of vector specification, all of the pins should be set. I pictured the pattern which mounts CPLD and decided pin arrangement.
032 -035	The signals to use in the inner logic are defined. 17 bits are needed by 100000 counts. The counter of 1/2 doesn't have to make a vector because it is 1 bit but vector specification is done to do an arithmetic operation. IN_DATA is the inner signal definition to tie the input of the 3-8 decoder.
039	The register of the inner logic is connected to the output register.
040	A NAND circuit on the side of set (S) is made.
041	A NAND circuit on the side of reset (R) is made.
042	The output on the side of the reset is connected with the input on the side of the set.
043	The output on the side of the set is connected with the input on the side of the reset.
046	The register of the 1/2 counter is connected with the output register.
047	It makes an input signal CLK_10M and a process is begun.
048	A change of CLK_10M from "0" to "1" is detected. "CLK_10M='1' and CLK_10M'event" is the description which detects that CLK_10M changed into '1' from '0'.
049 -051	A counter is cleared if Q100K become 99999. It is 100000 counts at 99999 because it starts from 0. 1/2 counter (QCLK) is added at the same time. Because QCLK is 1 bit, it repeats "0" and "1" alternately every time it counts in 100000. So, the output of the 1/2 counter is 1/200000.
053	When Q100K is not 100000, a counter is increased.
059	The input (A,B,C) of the 3-8 decoder is converted into the vector.
060	It makes an input signal IN_DATA and a process is begun.
061 -069	It is branched in the CASE sentence by the contents of IN_DATA. The data which matches input is output to DEC.
070	All conditions must be specified by the Case sentence. It becomes a syntax error when not specifying "when others =>" even if it specifies all conditions. The case of "when others =>" doesn't occur. So, X(Either of 0 or 1 is OK) is designated to the output.