XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: encoder1 Date: 7-20-2000, 8:28PM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
10 /36 ( 27%) 38 /180 ( 21%) 3 /36 ( 8%) 12 /34 ( 35%) 14 /72 ( 19%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 8 8 | I/O : 12 16
Output : 4 4 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 12 12
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 3
Non-registered Macrocell driving I/O 1
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 10 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 10 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
$OpTx$FX_DC$10 4 4 FB2_18 STD (b) (b)
I_q_0/I_q_0_RSTF 4 8 FB2_17 STD 25 I/O (b)
I_q_0/I_q_0_SETF 4 8 FB2_16 STD 26 I/O (b)
I_q_1/I_q_1_SETF 4 8 FB2_15 STD 27 I/O (b)
I_q_2/I_q_2_RSTF 4 8 FB2_14 STD 28 I/O (b)
I_q_2/I_q_2_SETF 4 8 FB2_13 STD 29 I/O (b)
error 8 8 FB2_4 STD FAST 43 I/O O
q<0> 2 2 FB1_2 STD FAST 3 I/O O
q<1> 2 6 FB2_11 STD FAST 34 I/O O
q<2> 2 2 FB1_11 STD FAST 13 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
D FB2_10 35 I/O I
G FB2_8 37 I/O I
a FB1_8 9 I/O I
b FB1_9 11 I/O I
c FB2_9 36 I/O I
e FB1_6 8 I/O I
f FB1_10 12 I/O I
h FB2_7 38 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 2 4 4 4 2/0 17
FB2 8 10 10 34 2/0 17
---- ----- ----- -----
10 38 4/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
q<0> 2 0 0 3 FB1_2 STD 3 I/O O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O
(unused) 0 0 0 5 FB1_4 4 I/O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
(unused) 0 0 0 5 FB1_6 8 I/O I
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
(unused) 0 0 0 5 FB1_8 9 I/O I
(unused) 0 0 0 5 FB1_9 11 I/O I
(unused) 0 0 0 5 FB1_10 12 I/O I
q<2> 2 0 0 3 FB1_11 STD 13 I/O O
(unused) 0 0 0 5 FB1_12 14 I/O
(unused) 0 0 0 5 FB1_13 18 I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 22 I/O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: "I_q_0/I_q_0_RSTF"
3: "I_q_2/I_q_2_RSTF"
4: "I_q_2/I_q_2_SETF"
2: "I_q_0/I_q_0_SETF"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q<0> XX...................................... 2 2
q<2> ..XX.................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 10/26
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O
(unused) 0 0 0 5 FB2_2 44 I/O
(unused) 0 0 \/2 3 FB2_3 42 GTS/I/O (b)
error 8 3<- 0 0 FB2_4 STD 43 I/O O
(unused) 0 0 /\1 4 FB2_5 40 GTS/I/O (b)
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
(unused) 0 0 0 5 FB2_7 38 I/O I
(unused) 0 0 0 5 FB2_8 37 I/O I
(unused) 0 0 0 5 FB2_9 36 I/O I
(unused) 0 0 0 5 FB2_10 35 I/O I
q<1> 2 0 0 3 FB2_11 STD 34 I/O O
(unused) 0 0 0 5 FB2_12 33 I/O
I_q_2/I_q_2_SETF 4 0 0 1 FB2_13 STD 29 I/O (b)
I_q_2/I_q_2_RSTF 4 0 0 1 FB2_14 STD 28 I/O (b)
I_q_1/I_q_1_SETF 4 0 0 1 FB2_15 STD 27 I/O (b)
I_q_0/I_q_0_SETF 4 0 0 1 FB2_16 STD 26 I/O (b)
I_q_0/I_q_0_RSTF 4 0 0 1 FB2_17 STD 25 I/O (b)
$OpTx$FX_DC$10 4 0 0 1 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$10" 5: a 8: e
2: D 6: b 9: f
3: G 7: c 10: h
4: "I_q_1/I_q_1_SETF"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
error .XX.XXXXXX.............................. 8 8
q<1> XXXX..X..X.............................. 6 6
I_q_2/I_q_2_SETF .XX.XXXXXX.............................. 8 8
I_q_2/I_q_2_RSTF .XX.XXXXXX.............................. 8 8
I_q_1/I_q_1_SETF .XX.XXXXXX.............................. 8 8
I_q_0/I_q_0_SETF .XX.XXXXXX.............................. 8 8
I_q_0/I_q_0_RSTF .XX.XXXXXX.............................. 8 8
$OpTx$FX_DC$10 ....XX.XX............................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"$OpTx$FX_DC$10" = a * /b * /e * /f
+ /a * b * /e * /f
+ /a * /b * e * /f
+ /a * /b * /e * f
"q<0>" := Gnd
"q<0>".CLKF = Gnd
"q<0>".SETF = "I_q_0/I_q_0_SETF"
"q<0>".RSTF = "I_q_0/I_q_0_RSTF"
"q<0>".PRLD = GND
"I_q_0/I_q_0_RSTF" = a * /b * /c * /D * /e * /f * /G * /h
+ /a * /b * c * /D * /e * /f * /G * /h
+ /a * /b * /c * /D * e * /f * /G * /h
+ /a * /b * /c * /D * /e * /f * G * /h
"I_q_0/I_q_0_SETF" = /a * b * /c * /D * /e * /f * /G * /h
+ /a * /b * /c * D * /e * /f * /G * /h
+ /a * /b * /c * /D * /e * f * /G * /h
+ /a * /b * /c * /D * /e * /f * /G * h
"q<1>" := Gnd
"q<1>".CLKF = Gnd
"q<1>".SETF = "I_q_1/I_q_1_SETF"
"q<1>".RSTF = /c * /D * /G * /h * "$OpTx$FX_DC$10"
"q<1>".PRLD = GND
"I_q_1/I_q_1_SETF" = /a * /b * c * /D * /e * /f * /G * /h
+ /a * /b * /c * D * /e * /f * /G * /h
+ /a * /b * /c * /D * /e * /f * G * /h
+ /a * /b * /c * /D * /e * /f * /G * h
"q<2>" := Gnd
"q<2>".CLKF = Gnd
"q<2>".SETF = "I_q_2/I_q_2_SETF"
"q<2>".RSTF = "I_q_2/I_q_2_RSTF"
"q<2>".PRLD = GND
"I_q_2/I_q_2_RSTF" = a * /b * /c * /D * /e * /f * /G * /h
+ /a * b * /c * /D * /e * /f * /G * /h
+ /a * /b * c * /D * /e * /f * /G * /h
+ /a * /b * /c * D * /e * /f * /G * /h
"I_q_2/I_q_2_SETF" = /a * /b * /c * /D * e * /f * /G * /h
+ /a * /b * /c * /D * /e * f * /G * /h
+ /a * /b * /c * /D * /e * /f * G * /h
+ /a * /b * /c * /D * /e * /f * /G * h
/error = a * /b * /c * /D * /e * /f * /G * /h
+ /a * /b * /c * D * /e * /f * /G * /h
+ /a * /b * /c * /D * /e * f * /G * /h
+ /a * /b * /c * /D * /e * /f * G * /h
+ /a * /b * /c * /D * /e * /f * /G * h
;Imported pterms FB2_3
+ /a * /b * c * /D * /e * /f * /G * /h
+ /a * /b * /c * /D * e * /f * /G * /h
;Imported pterms FB2_5
+ /a * b * /c * /D * /e * /f * /G * /h
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
e
q r
T T T < T T T r T V T
I I I 0 I I I o I C I
E E E > E E E r E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | TIE
e | 8 38 | h
a | 9 37 | G
GND | 10 36 | c
b | 11 XC9536-15-PC44 35 | D
f | 12 34 | q<1>
q<2> | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | TIE
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
T T T V T G T T T T T
I I I C I N I I I I I
E E E C E D E E E E E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : OFF
Global Set/Reset(GSR) Optimization : OFF
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
