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XACT:  version D.19                              Xilinx Inc.
                                  Fitter Report
Design Name: ud_counter1                         Date:  7- 9-2000,  6:18PM
Device Used: XC9536-15-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
4  /36  ( 11%) 23  /180  ( 12%) 4  /36  ( 11%) 13 /34  ( 38%) 13 /72  ( 18%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    9           9    |  I/O              :    13       15
Output        :    0           0    |  GCK/IO           :     0        3
Bidirectional :    4           4    |  GTS/IO           :     0        2
GCK           :    0           0    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     13          13

MACROCELL RESOURCES:

Total Macrocells Available                    36
Registered Macrocells                          4
Non-registered Macrocell driving I/O           0

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 4 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 4 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
q<0>                5       6       FB1_9   STD  FAST 11   I/O       I/O
q<1>                6       8       FB1_10  STD  FAST 12   I/O       I/O
q<2>                6       9       FB1_11  STD  FAST 13   I/O       I/O
q<3>                6       10      FB1_12  STD  FAST 14   I/O       I/O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
ce                                  FB1_4             4    I/O       I
clear                               FB1_1             2    I/O       I
clk                                 FB2_1             1    I/O       I
din<0>                              FB2_10            35   I/O       I
din<1>                              FB2_9             36   I/O       I
din<2>                              FB2_8             37   I/O       I
din<3>                              FB2_7             38   I/O       I
load                                FB1_2             3    I/O       I
up                                  FB1_6             8    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           4          13          13           23         0/4       17   
FB2           0           0           0            0         0/0       17   
            ----                                -----       -----     ----- 
              4                                   23         0/4       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               13/23
Number of signals used by logic mapping into function block:  13
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1         2     I/O     I
(unused)              0       0     0   5     FB1_2         3     I/O     I
(unused)              0       0     0   5     FB1_3         5     GCK/I/O 
(unused)              0       0     0   5     FB1_4         4     I/O     I
(unused)              0       0     0   5     FB1_5         6     GCK/I/O 
(unused)              0       0     0   5     FB1_6         8     I/O     I
(unused)              0       0     0   5     FB1_7         7     GCK/I/O 
(unused)              0       0   \/1   4     FB1_8         9     I/O     (b)
q<0>                  5       1<- \/1   0     FB1_9   STD   11    I/O     I/O
q<1>                  6       1<-   0   0     FB1_10  STD   12    I/O     I/O
q<2>                  6       1<-   0   0     FB1_11  STD   13    I/O     I/O
q<3>                  6       2<- /\1   0     FB1_12  STD   14    I/O     I/O
(unused)              0       0   /\2   3     FB1_13        18    I/O     (b)
(unused)              0       0     0   5     FB1_14        19    I/O     
(unused)              0       0     0   5     FB1_15        20    I/O     
(unused)              0       0     0   5     FB1_16        22    I/O     
(unused)              0       0     0   5     FB1_17        24    I/O     
(unused)              0       0     0   5     FB1_18              (b)     

Signals Used by Logic in Function Block
  1: ce                 6: "din<2>"          10: "q<1>" 
  2: clear              7: "din<3>"          11: "q<2>" 
  3: clk                8: load              12: "q<3>" 
  4: "din<0>"           9: "q<0>"            13: up 
  5: "din<1>"         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q<0>                 XXXX...XX............................... 6       6
q<1>                 XXX.X..XXX..X........................... 8       8
q<2>                 XXX..X.XXXX.X........................... 9       9
q<3>                 XXX...XXXXXXX........................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1         1     I/O     I
(unused)              0       0     0   5     FB2_2         44    I/O     
(unused)              0       0     0   5     FB2_3         42    GTS/I/O 
(unused)              0       0     0   5     FB2_4         43    I/O     
(unused)              0       0     0   5     FB2_5         40    GTS/I/O 
(unused)              0       0     0   5     FB2_6         39    GSR/I/O 
(unused)              0       0     0   5     FB2_7         38    I/O     I
(unused)              0       0     0   5     FB2_8         37    I/O     I
(unused)              0       0     0   5     FB2_9         36    I/O     I
(unused)              0       0     0   5     FB2_10        35    I/O     I
(unused)              0       0     0   5     FB2_11        34    I/O     
(unused)              0       0     0   5     FB2_12        33    I/O     
(unused)              0       0     0   5     FB2_13        29    I/O     
(unused)              0       0     0   5     FB2_14        28    I/O     
(unused)              0       0     0   5     FB2_15        27    I/O     
(unused)              0       0     0   5     FB2_16        26    I/O     
(unused)              0       0     0   5     FB2_17        25    I/O     
(unused)              0       0     0   5     FB2_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 "q<0>"  :=  load * "din<0>"
	+ /load * /ce * "q<0>".PIN
;Imported pterms FB1_8
	+ /load * ce * /"q<0>".PIN
    "q<0>".CLKF  =  clk
    "q<0>".RSTF  =  clear
    "q<0>".PRLD  =  GND    

 "q<1>".T  =  load * "din<1>" * /"q<1>".PIN
	+ /load * ce * up * "q<0>".PIN
	+ /load * ce * /up * /"q<0>".PIN
;Imported pterms FB1_9
	+ load * /"din<1>" * "q<1>".PIN
    "q<1>".CLKF  =  clk
    "q<1>".RSTF  =  clear
    "q<1>".PRLD  =  GND    

 "q<2>".T  =  load * "din<2>" * /"q<2>".PIN
	+ /load * ce * up * "q<0>".PIN * "q<1>".PIN
	+ /load * ce * /up * /"q<0>".PIN * /"q<1>".PIN
;Imported pterms FB1_12
	+ load * /"din<2>" * "q<2>".PIN
    "q<2>".CLKF  =  clk
    "q<2>".RSTF  =  clear
    "q<2>".PRLD  =  GND    

 "q<3>".T  =  /load * ce * up * "q<0>".PIN * "q<1>".PIN * 
	"q<2>".PIN
	+ /load * ce * /up * /"q<0>".PIN * /"q<1>".PIN * 
	/"q<2>".PIN
;Imported pterms FB1_13
	+ load * "din<3>" * /"q<3>".PIN
	+ load * /"din<3>" * "q<3>".PIN
    "q<3>".CLKF  =  clk
    "q<3>".RSTF  =  clear
    "q<3>".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9536-15-PC44


                   c                    
                l  l                    
       T  T     o  e  c  T  T  T  V  T  
       I  I  c  a  a  l  I  I  I  C  I  
       E  E  e  d  r  k  E  E  E  C  E  
       --------------------------------  
      /6  5  4  3  2  1  44 43 42 41 40 \
 TIE | 7                             39 | TIE
  up | 8                             38 | din<3>
 TIE | 9                             37 | din<2>
 GND | 10                            36 | din<1>
q<0> | 11        XC9536-15-PC44      35 | din<0>
q<1> | 12                            34 | TIE
q<2> | 13                            33 | TIE
q<3> | 14                            32 | VCC
 TDI | 15                            31 | GND
 TMS | 16                            30 | TDO
 TCK | 17                            29 | TIE
     \ 18 19 20 21 22 23 24 25 26 27 28 /
       --------------------------------  
       T  T  T  V  T  G  T  T  T  T  T  
       I  I  I  C  I  N  I  I  I  I  I  
       E  E  E  C  E  D  E  E  E  E  E  


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9536-15-PC44
Use Timing Constraints                      : ON
Ignore Assignments In Design File           : OFF
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : OFF
Global Set/Reset(GSR) Optimization          : OFF
Global Output Enable(GTS) Optimization      : OFF
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36