Signal racing is the condition when two or more signals change almost simultaneously. The condition may cause glitches or spikes in the output signal as shown in figure 7.6. The effects of these glitches can be eliminated by using synchronous timing techniques. In synchronous timing the glitches are allowed to come and go, and the logic state changes are initiated by a timing pulse (clock pulse).
Figure 7.6: a) A timing diagram for the EOR circuit. b) An expanded view of the glitch shows it to be caused by a signal race condition.