Delay X cycles (7-263) for 18F chips by Scott Dattalo

Code:

• Here's a delay routine optimized for the 18f family that delays exactly
  7+N cycles, were N is a value passed in W. It uses no look up tables (like
  similar routines for other devices), requires no extra RAM, and is only 7
  instructions.
  
  ;------------------------------------------------------------
  ; DelayCycles:
  ;
  ; Input:   W -- the desired delay
  ; Output:  Returns after W+7 cycles
  
  DelayCycles:
  
  dc1:        ADDLW        -3        ;3-cycle delay loop
         BC        dc1
  
   ; W now contains either -3 (0xFD), -2 (0xFE) or -1 (0xFF).
   ; The -2 case needs to be delayed an extra cycle more than
   ; the -3 case, and the -1 case needs yet another cycle of delay.
   ;
   ; Examine the bottom two bits of W to determine the exact delay
   ;
  
         BTFSS   WREG,1
          BRA        dc2        ;W=0xFD - no extra delay needed
         RRCF        WREG,F  ;If the LSB is set (W=0xFF) then set C
         BC        dc2     ;add a cycle delay for W=0xFF but not 0xFE
  dc2:    RETURN
  
  
  Pic code... Just like the good ol' days!
  
  Scott

  +

Archive:

• PICList post "18F delay" +

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