layers of a PWB (PCB)

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layer stackup

layer stackup information.

See layer stack-up text

• If it's important that your board is fabricated with the exact layer stackup you specified in the ``Layer Stack Manager'', you can create a ``Layer Stackup Legend'' in the layout.

  (paraphrased from Geoff Harland 2001-07-08 7:24:00 PM)

  • Set up layer information in ``Design | Layer Stack Manager...''. OK.
  • Which layer do you want the legend to be on ? Make that layer the current/active layer.
  • Choose ``Tools | Layer Stackup Legend''
  • Click on the PCB to select one corner.
  • (!!) Press the Tab key. This brings up a dialog box with lots of checkbox details.
  • Click on the PCB to select the second corner

  Now the layer stackup information should be visible on the layout.

• "Abd ul-Rahman Lomax" on 2001-06-17 02:40:17 AM My favorite stackup is still:

  1 signal (fat traces)
  2 signal
  3 power
  4 ground
  5 signal
  6 signal
  

  A variation on this is that layers 1 and 6 are poured with ground/power copper, and/or 2 and 5, but this can get complicated. Abdulrahman Lomax

• [general PWB design] With a 0.8mm pitch uBGA (micro ball grid array), Up to 48 pins on a full array you can route out completely on the top side with 5 mil traces, but we automatically go to microvias as soon as the pin count exceeds 48. -- John Bradley Alcatel USA Plano, TX

  "Schwartz, Jerome"  on 2001-01-10 09:22:56 AM
  To:	"DesignerCouncil E-Mail Forum." 
  Subject:	Re: [DC] Routing suggestions on 0.8mm uBGA
  
  
  I recently did a design having 4 BGA's. Two were
  .8mm and two were .75mm. This is what I used after I talked
  with our manufacturing people and several fab shops.
  
  (My units are in inches)
  
  BGA PAD = .013"
  Solder mask opening = .019"
  Paste screen opening = .015"
  
  VIA = .017"
  FINISHED HOLE = .006"
  
  Traces on outer layer connecting BGA PAD to VIA = .006"
  
  Inner layer traces = .004"
  SPACE (Trace to via) = .0048"
  
  90 degree breakout and or tangency was allowed. As in the spec.
  Filleting was required.
  Vias were tented.
  Via holes can be filled but only 100%. Checked by x-ray.
  My board thickness was .060".
  This was a blind via card but all BGA vias were through hole.
  Aspect ratio was 6:1.
  
  We have built about 120 of these with no problems in the BGA's.
  
  
  
  Regards,
  
                  Jerry Schwartz, CID
                  IPC Certified Interconnect Designer
                  "May the Schwartz be with you"
  
  Jerry Schwartz, CID             Designer 3
  Harris Corporation GCSD         Voice (321)-727-5474
  P.O. Box 37, MS 1/9843          Fax   (321)-729-5990
  Melbourne, FL 32902-0037        Pager (321)-690-9797
  
  http://harris.com
  
  
  
  
  
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  Search previous postings at: www.ipc.org > On-Line Resources & Databases >
  E-mail Archives
  Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
  information, or contact Keach Sasamori at sasako @ ipc.org
  
  
  
  

• Q: How do I delete power planes ? When I just hit delete, Protel will remove the plane of the list temporarily -- but when I get back to Layer Stack Manager, the power plane will still be there. (``I hated that'' -- Phan Le).
  A: 1. Delete everything on that plane layer (strings, ``track'', split planes, ... everything. Leave the multilayer and the stuff on the multilayer alone -- just delete the stuff on this plane layer.). 2. In the stack manager, change the net assigned to that plane to ``No Net''. 3. Delete the plane in the stack manager [paraphrased] -- Geoff Harland
• Ray Humphrey on 2001-04-05 02:24:37 AM wrote: To: "DesignerCouncil E-Mail Forum." Subject: Re: [DC] Blind and Buried Vias Mitch, On our high-speed boards, power is not on a plane; it is routed (usually, on it's own layer) in a 'star' strategy, with individual lines supplying power to different parts of the circuit. Ground is on a plane and is, usually, the 2nd layer down. Since micro vias require such a low aspect ratio (we maintain ~ .7:1 or less), designing a board with 50-100 ohm micro-strip lines is a real challenge, especially, if you also need to need to maintain trace width => 10 mils! This is our current configuration for 50-ohm, controlled impedance on the top layer combined with 8-mil blind vias in CSP pads. Our CSPs are .5 mm (19.7 mil) pitch with .3 mm (11.8 mil) pads. For PCBs that have CSP with only ground pads on the inside - 4-layer PCB Layer 2 is a ground plane 50-ohm line width = ~ 10 mils 8-mil layer 1 to layer 2 blind via Layer 1 base copper thickness = .7 mils Dielectric thickness, layer 1 to layer 2 = 4.6 mils 4.6 + .7 = 5.3 mils - therefore, 5.3 / 8 = .6625:1 aspect ratio 14-mil CSP pads with 8-mil blind micro vias in ground pads (pad size must be 6 over hole size for micro vias, 10 over for mechanical drill). We actually would like to have 12-mil CSP pads but had to increase their size to accommodate the 8-mil via, since we need the increased dielectric thickness in order to keep our line width up to 10 mils at 50 ohms. Sheesh! Gets tiring just typing it! :) For PCBs that have CSP with signal pads on the inside - 6-layer PCB Layer 2 is a signal layer for signals out of the center of the CSP Layer 3 is a ground plane 50-ohm line width = ~ 12.25 mils 5-mil layer 1 to layer 2 blind via 8-mil layer 1 to layer 3 blind via Layer 1 base copper thickness = .7 mils Layer 2 copper thickness = .7 mils Dielectric thickness, layer 1 to layer 2 and layer 5 to layer 6 = 2.3 mils Dielectric thickness, layer 2 to layer 3 and layer 4 to layer 5 = 2.3 mils Layer 1 to 2 - 2.3 + .7 = 3 mils - therefore, 3 / 5 = .6:1 aspect ratio Layer 1 to 3 - 2.3 + 2.3 + .7 + .7 = 6 mils - therefore, 6 / 8 = .75:1 aspect ratio In this case, 6 layers are necessary in order to keep from splitting up the ground plane directly under the CSP. Splitting the ground plane up with signal lines from the center of the CSP can create an antenna effect at higher (GHz) frequencies. I hope this has been of some help to you and/or some others. If you need additional help, please contact me with direct email. Ray -----

end http://massmind.org/techref/pwb_layers.htm

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