[Menu]>[CPLD]>[7 x 16 Latch Register]


Fitting report
for 7 x 16 Latch Register ( Side B )



XACT:  version D.19                              Xilinx Inc.
                                  Fitter Report
Design Name: latch_b                             Date:  7-22-2000,  9:07PM
Device Used: XC9572-15-PC84
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
56 /72  ( 77%) 168 /360  ( 46%) 56 /72  ( 77%) 68 /69  ( 98%) 103/144 ( 71%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   12          12    |  I/O              :    62        1
Output        :   56          56    |  GCK/IO           :     3        0
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     68          68

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                         56
Non-registered Macrocell driving I/O           0

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 56 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 56 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
q08<0>              3       7       FB3_7   STD  FAST 35   I/O       O
q08<1>              3       7       FB3_15  STD  FAST 37   I/O       O
q08<2>              3       7       FB3_10  STD  FAST 40   I/O       O
q08<3>              3       7       FB3_17  STD  FAST 39   I/O       O
q08<4>              3       7       FB3_12  STD  FAST 41   I/O       O
q08<5>              3       7       FB4_2   STD  FAST 44   I/O       O
q08<6>              3       7       FB3_13  STD  FAST 43   I/O       O
q09<0>              3       7       FB4_1   STD  FAST 46   I/O       O
q09<1>              3       7       FB3_16  STD  FAST 45   I/O       O
q09<2>              3       7       FB4_8   STD  FAST 48   I/O       O
q09<3>              3       7       FB4_5   STD  FAST 47   I/O       O
q09<4>              3       7       FB4_9   STD  FAST 50   I/O       O
q09<5>              3       7       FB4_4   STD  FAST 52   I/O       O
q09<6>              3       7       FB4_7   STD  FAST 55   I/O       O
q10<0>              3       7       FB4_13  STD  FAST 61   I/O       O
q10<1>              3       7       FB2_1   STD  FAST 63   I/O       O
q10<2>              3       7       FB4_15  STD  FAST 65   I/O       O
q10<3>              3       7       FB2_3   STD  FAST 67   I/O       O
q10<4>              3       7       FB2_2   STD  FAST 69   I/O       O
q10<5>              3       7       FB2_6   STD  FAST 71   I/O       O
q10<6>              3       7       FB2_7   STD  FAST 76   GTS/I/O   O
q11<0>              3       7       FB2_17  STD  FAST 84   I/O       O
q11<1>              3       7       FB2_15  STD  FAST 83   I/O       O
q11<2>              3       7       FB2_16  STD  FAST 82   I/O       O
q11<3>              3       7       FB2_14  STD  FAST 81   I/O       O
q11<4>              3       7       FB2_13  STD  FAST 80   I/O       O
q11<5>              3       7       FB2_12  STD  FAST 79   I/O       O
q11<6>              3       7       FB2_11  STD  FAST 77   GTS/I/O   O
q12<0>              3       7       FB1_4   STD  FAST 7    I/O       O
q12<1>              3       7       FB1_3   STD  FAST 6    I/O       O
q12<2>              3       7       FB1_8   STD  FAST 5    I/O       O
q12<3>              3       7       FB1_1   STD  FAST 4    I/O       O
q12<4>              3       7       FB1_6   STD  FAST 3    I/O       O
q12<5>              3       7       FB1_5   STD  FAST 2    I/O       O
q12<6>              3       7       FB1_2   STD  FAST 1    I/O       O
q13<0>              3       7       FB1_17  STD  FAST 15   I/O       O
q13<1>              3       7       FB1_15  STD  FAST 14   I/O       O
q13<2>              3       7       FB1_14  STD  FAST 12   GCK/I/O   O
q13<3>              3       7       FB1_10  STD  FAST 13   I/O       O
q13<4>              3       7       FB1_7   STD  FAST 11   I/O       O
q13<5>              3       7       FB1_11  STD  FAST 10   GCK/I/O   O
q13<6>              3       7       FB1_9   STD  FAST 9    GCK/I/O   O
q14<0>              3       7       FB1_18  STD  FAST 24   I/O       O
q14<1>              3       7       FB1_16  STD  FAST 23   I/O       O
q14<2>              3       7       FB3_8   STD  FAST 21   I/O       O
q14<3>              3       7       FB1_13  STD  FAST 20   I/O       O
q14<4>              3       7       FB3_5   STD  FAST 19   I/O       O
q14<5>              3       7       FB1_12  STD  FAST 18   I/O       O
q14<6>              3       7       FB3_2   STD  FAST 17   I/O       O
q15<0>              3       7       FB3_14  STD  FAST 36   I/O       O
q15<1>              3       7       FB3_11  STD  FAST 33   I/O       O
q15<2>              3       7       FB3_6   STD  FAST 34   I/O       O
q15<3>              3       7       FB3_4   STD  FAST 32   I/O       O
q15<4>              3       7       FB3_3   STD  FAST 31   I/O       O
q15<5>              3       7       FB3_9   STD  FAST 26   I/O       O
q15<6>              3       7       FB3_1   STD  FAST 25   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clk                                 FB2_10            75   I/O       I
din<0>                              FB4_17            66   I/O       I
din<1>                              FB4_16            62   I/O       I
din<2>                              FB4_12            58   I/O       I
din<3>                              FB4_14            56   I/O       I
din<4>                              FB4_6             54   I/O       I
din<5>                              FB4_11            53   I/O       I
din<6>                              FB4_3             51   I/O       I
s<0>                                FB2_9             74   GSR/I/O   I
s<1>                                FB2_8             72   I/O       I
s<2>                                FB2_5             70   I/O       I
s<3>                                FB2_4             68   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          18          30          30           54        18/0       18   
FB2          12          24          24           36        12/0       17   
FB3          17          29          29           51        17/0       17   
FB4           9          20          20           27         9/0       17   
            ----                                -----       -----     ----- 
             56                                  168        56/0       69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               30/6
Number of signals used by logic mapping into function block:  30
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
q12<3>                3       0     0   2     FB1_1   STD   4     I/O     O
q12<6>                3       0     0   2     FB1_2   STD   1     I/O     O
q12<1>                3       0     0   2     FB1_3   STD   6     I/O     O
q12<0>                3       0     0   2     FB1_4   STD   7     I/O     O
q12<5>                3       0     0   2     FB1_5   STD   2     I/O     O
q12<4>                3       0     0   2     FB1_6   STD   3     I/O     O
q13<4>                3       0     0   2     FB1_7   STD   11    I/O     O
q12<2>                3       0     0   2     FB1_8   STD   5     I/O     O
q13<6>                3       0     0   2     FB1_9   STD   9     GCK/I/O O
q13<3>                3       0     0   2     FB1_10  STD   13    I/O     O
q13<5>                3       0     0   2     FB1_11  STD   10    GCK/I/O O
q14<5>                3       0     0   2     FB1_12  STD   18    I/O     O
q14<3>                3       0     0   2     FB1_13  STD   20    I/O     O
q13<2>                3       0     0   2     FB1_14  STD   12    GCK/I/O O
q13<1>                3       0     0   2     FB1_15  STD   14    I/O     O
q14<1>                3       0     0   2     FB1_16  STD   23    I/O     O
q13<0>                3       0     0   2     FB1_17  STD   15    I/O     O
q14<0>                3       0     0   2     FB1_18  STD   24    I/O     O

Signals Used by Logic in Function Block
  1: clk               11: "q12<2>".LFBK     21: "q13<5>".LFBK 
  2: "din<0>"          12: "q12<3>".LFBK     22: "q13<6>".LFBK 
  3: "din<1>"          13: "q12<4>".LFBK     23: "q14<0>".LFBK 
  4: "din<2>"          14: "q12<5>".LFBK     24: "q14<1>".LFBK 
  5: "din<3>"          15: "q12<6>".LFBK     25: "q14<3>".LFBK 
  6: "din<4>"          16: "q13<0>".LFBK     26: "q14<5>".LFBK 
  7: "din<5>"          17: "q13<1>".LFBK     27: "s<0>" 
  8: "din<6>"          18: "q13<2>".LFBK     28: "s<1>" 
  9: "q12<0>"          19: "q13<3>".LFBK     29: "s<2>" 
 10: "q12<1>".LFBK     20: "q13<4>".LFBK     30: "s<3>" 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q12<3>               X...X......X..............XXXX.......... 7       7
q12<6>               X......X......X...........XXXX.......... 7       7
q12<1>               X.X......X................XXXX.......... 7       7
q12<0>               XX......X.................XXXX.......... 7       7
q12<5>               X.....X......X............XXXX.......... 7       7
q12<4>               X....X......X.............XXXX.......... 7       7
q13<4>               X....X.............X......XXXX.......... 7       7
q12<2>               X..X......X...............XXXX.......... 7       7
q13<6>               X......X.............X....XXXX.......... 7       7
q13<3>               X...X.............X.......XXXX.......... 7       7
q13<5>               X.....X.............X.....XXXX.......... 7       7
q14<5>               X.....X..................XXXXX.......... 7       7
q14<3>               X...X...................X.XXXX.......... 7       7
q13<2>               X..X.............X........XXXX.......... 7       7
q13<1>               X.X.............X.........XXXX.......... 7       7
q14<1>               X.X....................X..XXXX.......... 7       7
q13<0>               XX.............X..........XXXX.......... 7       7
q14<0>               XX....................X...XXXX.......... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               24/12
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
q10<1>                3       0     0   2     FB2_1   STD   63    I/O     O
q10<4>                3       0     0   2     FB2_2   STD   69    I/O     O
q10<3>                3       0     0   2     FB2_3   STD   67    I/O     O
(unused)              0       0     0   5     FB2_4         68    I/O     I
(unused)              0       0     0   5     FB2_5         70    I/O     I
q10<5>                3       0     0   2     FB2_6   STD   71    I/O     O
q10<6>                3       0     0   2     FB2_7   STD   76    GTS/I/O O
(unused)              0       0     0   5     FB2_8         72    I/O     I
(unused)              0       0     0   5     FB2_9         74    GSR/I/O I
(unused)              0       0     0   5     FB2_10        75    I/O     I
q11<6>                3       0     0   2     FB2_11  STD   77    GTS/I/O O
q11<5>                3       0     0   2     FB2_12  STD   79    I/O     O
q11<4>                3       0     0   2     FB2_13  STD   80    I/O     O
q11<3>                3       0     0   2     FB2_14  STD   81    I/O     O
q11<1>                3       0     0   2     FB2_15  STD   83    I/O     O
q11<2>                3       0     0   2     FB2_16  STD   82    I/O     O
q11<0>                3       0     0   2     FB2_17  STD   84    I/O     O
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: clk                9: "q10<1>".LFBK     17: "q11<3>".LFBK 
  2: "din<0>"          10: "q10<3>".LFBK     18: "q11<4>".LFBK 
  3: "din<1>"          11: "q10<4>".LFBK     19: "q11<5>".LFBK 
  4: "din<2>"          12: "q10<5>".LFBK     20: "q11<6>".LFBK 
  5: "din<3>"          13: "q10<6>".LFBK     21: "s<0>" 
  6: "din<4>"          14: "q11<0>".LFBK     22: "s<1>" 
  7: "din<5>"          15: "q11<1>".LFBK     23: "s<2>" 
  8: "din<6>"          16: "q11<2>".LFBK     24: "s<3>" 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q10<1>               X.X.....X...........XXXX................ 7       7
q10<4>               X....X....X.........XXXX................ 7       7
q10<3>               X...X....X..........XXXX................ 7       7
q10<5>               X.....X....X........XXXX................ 7       7
q10<6>               X......X....X.......XXXX................ 7       7
q11<6>               X......X...........XXXXX................ 7       7
q11<5>               X.....X...........X.XXXX................ 7       7
q11<4>               X....X...........X..XXXX................ 7       7
q11<3>               X...X...........X...XXXX................ 7       7
q11<1>               X.X...........X.....XXXX................ 7       7
q11<2>               X..X...........X....XXXX................ 7       7
q11<0>               XX...........X......XXXX................ 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
q15<6>                3       0     0   2     FB3_1   STD   25    I/O     O
q14<6>                3       0     0   2     FB3_2   STD   17    I/O     O
q15<4>                3       0     0   2     FB3_3   STD   31    I/O     O
q15<3>                3       0     0   2     FB3_4   STD   32    I/O     O
q14<4>                3       0     0   2     FB3_5   STD   19    I/O     O
q15<2>                3       0     0   2     FB3_6   STD   34    I/O     O
q08<0>                3       0     0   2     FB3_7   STD   35    I/O     O
q14<2>                3       0     0   2     FB3_8   STD   21    I/O     O
q15<5>                3       0     0   2     FB3_9   STD   26    I/O     O
q08<2>                3       0     0   2     FB3_10  STD   40    I/O     O
q15<1>                3       0     0   2     FB3_11  STD   33    I/O     O
q08<4>                3       0     0   2     FB3_12  STD   41    I/O     O
q08<6>                3       0     0   2     FB3_13  STD   43    I/O     O
q15<0>                3       0     0   2     FB3_14  STD   36    I/O     O
q08<1>                3       0     0   2     FB3_15  STD   37    I/O     O
q09<1>                3       0     0   2     FB3_16  STD   45    I/O     O
q08<3>                3       0     0   2     FB3_17  STD   39    I/O     O
(unused)              0       0     0   5     FB3_18              (b)     

Signals Used by Logic in Function Block
  1: clk               11: "q08<2>".LFBK     21: "q15<2>".LFBK 
  2: "din<0>"          12: "q08<3>".LFBK     22: "q15<3>".LFBK 
  3: "din<1>"          13: "q08<4>".LFBK     23: "q15<4>".LFBK 
  4: "din<2>"          14: "q08<6>".LFBK     24: "q15<5>".LFBK 
  5: "din<3>"          15: "q09<1>".LFBK     25: "q15<6>".LFBK 
  6: "din<4>"          16: "q14<2>".LFBK     26: "s<0>" 
  7: "din<5>"          17: "q14<4>".LFBK     27: "s<1>" 
  8: "din<6>"          18: "q14<6>".LFBK     28: "s<2>" 
  9: "q08<0>"          19: "q15<0>".LFBK     29: "s<3>" 
 10: "q08<1>".LFBK     20: "q15<1>".LFBK    

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q15<6>               X......X................XXXXX........... 7       7
q14<6>               X......X.........X.......XXXX........... 7       7
q15<4>               X....X................X..XXXX........... 7       7
q15<3>               X...X................X...XXXX........... 7       7
q14<4>               X....X..........X........XXXX........... 7       7
q15<2>               X..X................X....XXXX........... 7       7
q08<0>               XX......X................XXXX........... 7       7
q14<2>               X..X...........X.........XXXX........... 7       7
q15<5>               X.....X................X.XXXX........... 7       7
q08<2>               X..X......X..............XXXX........... 7       7
q15<1>               X.X................X.....XXXX........... 7       7
q08<4>               X....X......X............XXXX........... 7       7
q08<6>               X......X.....X...........XXXX........... 7       7
q15<0>               XX................X......XXXX........... 7       7
q08<1>               X.X......X...............XXXX........... 7       7
q09<1>               X.X...........X..........XXXX........... 7       7
q08<3>               X...X......X.............XXXX........... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               20/16
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
q09<0>                3       0     0   2     FB4_1   STD   46    I/O     O
q08<5>                3       0     0   2     FB4_2   STD   44    I/O     O
(unused)              0       0     0   5     FB4_3         51    I/O     I
q09<5>                3       0     0   2     FB4_4   STD   52    I/O     O
q09<3>                3       0     0   2     FB4_5   STD   47    I/O     O
(unused)              0       0     0   5     FB4_6         54    I/O     I
q09<6>                3       0     0   2     FB4_7   STD   55    I/O     O
q09<2>                3       0     0   2     FB4_8   STD   48    I/O     O
q09<4>                3       0     0   2     FB4_9   STD   50    I/O     O
(unused)              0       0     0   5     FB4_10        57    I/O     
(unused)              0       0     0   5     FB4_11        53    I/O     I
(unused)              0       0     0   5     FB4_12        58    I/O     I
q10<0>                3       0     0   2     FB4_13  STD   61    I/O     O
(unused)              0       0     0   5     FB4_14        56    I/O     I
q10<2>                3       0     0   2     FB4_15  STD   65    I/O     O
(unused)              0       0     0   5     FB4_16        62    I/O     I
(unused)              0       0     0   5     FB4_17        66    I/O     I
(unused)              0       0     0   5     FB4_18              (b)     

Signals Used by Logic in Function Block
  1: clk                8: "q08<5>".LFBK     15: "q10<0>".LFBK 
  2: "din<0>"           9: "q09<0>".LFBK     16: "q10<2>".LFBK 
  3: "din<2>"          10: "q09<2>".LFBK     17: "s<0>" 
  4: "din<3>"          11: "q09<3>".LFBK     18: "s<1>" 
  5: "din<4>"          12: "q09<4>".LFBK     19: "s<2>" 
  6: "din<5>"          13: "q09<5>".LFBK     20: "s<3>" 
  7: "din<6>"          14: "q09<6>".LFBK    

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
q09<0>               XX......X.......XXXX.................... 7       7
q08<5>               X....X.X........XXXX.................... 7       7
q09<5>               X....X......X...XXXX.................... 7       7
q09<3>               X..X......X.....XXXX.................... 7       7
q09<6>               X.....X......X..XXXX.................... 7       7
q09<2>               X.X......X......XXXX.................... 7       7
q09<4>               X...X......X....XXXX.................... 7       7
q10<0>               XX............X.XXXX.................... 7       7
q10<2>               X.X............XXXXX.................... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
    Omitting

****************************  Device Pin Out ****************************

Device : XC9572-15-PC84


         q  q  q     q  q  q  q  q  q  q  q  q  q  q  q  q     q  q     
         1  1  1     1  1  1  1  1  1  1  1  1  1  1  1  1     1  1     
         3  3  3     2  2  2  2  2  2  2  1  1  1  1  1  1     1  0     
         <  <  <  G  <  <  <  <  <  <  <  <  <  <  <  <  <  V  <  <  c  
         4  5  6  N  0  1  2  3  4  5  6  0  1  2  3  4  5  C  6  6  l  
         >  >  >  D  >  >  >  >  >  >  >  >  >  >  >  >  >  C  >  >  k  
         --------------------------------------------------------------  
        /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
q13<2> | 12                                                          74 | s<0>
q13<3> | 13                                                          73 | VCC
q13<1> | 14                                                          72 | s<1>
q13<0> | 15                                                          71 | q10<5>
   GND | 16                                                          70 | s<2>
q14<6> | 17                                                          69 | q10<4>
q14<5> | 18                                                          68 | s<3>
q14<4> | 19                                                          67 | q10<3>
q14<3> | 20                                                          66 | din<0>
q14<2> | 21                       XC9572-15-PC84                     65 | q10<2>
   VCC | 22                                                          64 | VCC
q14<1> | 23                                                          63 | q10<1>
q14<0> | 24                                                          62 | din<1>
q15<6> | 25                                                          61 | q10<0>
q15<5> | 26                                                          60 | GND
   GND | 27                                                          59 | TDO
   TDI | 28                                                          58 | din<2>
   TMS | 29                                                          57 | TIE
   TCK | 30                                                          56 | din<3>
q15<4> | 31                                                          55 | q09<6>
q15<3> | 32                                                          54 | din<4>
       \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
         --------------------------------------------------------------  
         q  q  q  q  q  V  q  q  q  G  q  q  q  q  q  q  G  q  d  q  d  
         1  1  0  1  0  C  0  0  0  N  0  0  0  0  0  0  N  0  i  0  i  
         5  5  8  5  8  C  8  8  8  D  8  8  9  9  9  9  D  9  n  9  n  
         <  <  <  <  <     <  <  <     <  <  <  <  <  <     <  <  <  <  
         1  2  0  0  1     3  2  4     6  5  1  0  3  2     4  6  5  5  
         >  >  >  >  >     >  >  >     >  >  >  >  >  >     >  >  >  >  


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-15-PC84
Use Timing Constraints                      : ON
Ignore Assignments In Design File           : OFF
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Guide File Used                             : NONE
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : OFF
Global Set/Reset(GSR) Optimization          : OFF
Global Output Enable(GTS) Optimization      : OFF
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36