On this page, I will introduce "5 Binary Counter" which was written in VHDL.
It repeats count up operation of five counts ( 0,1,2,3,4 ).
Like 000(0) -> 001(1) -> 010(2) -> 011(3) -> 100(4) -> 000(0) -> 001(1) ....
As the device, it deals with CPLD(XC9536-PC44).

In the logic this time, I am using GCK(Global Clocks) as the clock pulse input terminal
and GSR(Global Set/Reset) as the counter reset terminal for the practice of VHDL.

Source code and Explanation Fitting report Processing parameter specification

Operating state table Input Output Operation CLEAR CE CLK Q2,Q1,Q0 L X X 0,0,0 Counter clear H L Q = Q Count stop H H Q = Q+1 Count up H : High level L : Low level X : Don't care CLK is effective when changing into H from the L.