XACT: version D.19 Xilinx Inc.
Fitter Report
Design Name: counter5 Date: 7-20-2000, 8:27AM
Device Used: XC9536-15-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
3 /36 ( 8%) 5 /180 ( 2%) 3 /36 ( 8%) 6 /34 ( 17%) 4 /72 ( 5%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 1 1 | I/O : 4 24
Output : 0 0 | GCK/IO : 1 2
Bidirectional : 3 3 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 6 6
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 3
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
The complement of 'clear' mapped onto global set/reset net GSR1.
POWER DATA:
There are 3 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 3 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
q5<0> 2 4 FB1_9 STD FAST 11 I/O I/O
q5<1> 1 2 FB1_10 STD FAST 12 I/O I/O
q5<2> 2 4 FB1_11 STD FAST 13 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
ce FB2_1 1 I/O I
clear FB2_6 39 GSR/I/O GSR
clk FB1_3 5 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 3 4 4 5 0/3 17
FB2 0 0 0 0 0/0 17
---- ----- ----- -----
3 5 0/3 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 4/32
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O
(unused) 0 0 0 5 FB1_2 3 I/O
(unused) 0 0 0 5 FB1_3 5 GCK/I/O GCK
(unused) 0 0 0 5 FB1_4 4 I/O
(unused) 0 0 0 5 FB1_5 6 GCK/I/O
(unused) 0 0 0 5 FB1_6 8 I/O
(unused) 0 0 0 5 FB1_7 7 GCK/I/O
(unused) 0 0 0 5 FB1_8 9 I/O
q5<0> 2 0 0 3 FB1_9 STD 11 I/O I/O
q5<1> 1 0 0 4 FB1_10 STD 12 I/O I/O
q5<2> 2 0 0 3 FB1_11 STD 13 I/O I/O
(unused) 0 0 0 5 FB1_12 14 I/O
(unused) 0 0 0 5 FB1_13 18 I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 22 I/O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: ce 3: "q5<1>" 4: "q5<2>"
2: "q5<0>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
q5<0> XXXX.................................... 4 4
q5<1> XX...................................... 2 2
q5<2> XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O I
(unused) 0 0 0 5 FB2_2 44 I/O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O GSR
(unused) 0 0 0 5 FB2_7 38 I/O
(unused) 0 0 0 5 FB2_8 37 I/O
(unused) 0 0 0 5 FB2_9 36 I/O
(unused) 0 0 0 5 FB2_10 35 I/O
(unused) 0 0 0 5 FB2_11 34 I/O
(unused) 0 0 0 5 FB2_12 33 I/O
(unused) 0 0 0 5 FB2_13 29 I/O
(unused) 0 0 0 5 FB2_14 28 I/O
(unused) 0 0 0 5 FB2_15 27 I/O
(unused) 0 0 0 5 FB2_16 26 I/O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
/"q5<0>".T = /ce
+ /"q5<0>".PIN * /"q5<1>".PIN * "q5<2>".PIN
"q5<0>".CLKF = clk ;FCLK/GCK
"q5<0>".RSTF = /clear ;GSR
"q5<0>".PRLD = GND
"q5<1>".T = ce * "q5<0>".PIN
"q5<1>".CLKF = clk ;FCLK/GCK
"q5<1>".RSTF = /clear ;GSR
"q5<1>".PRLD = GND
"q5<2>".T = ce * "q5<0>".PIN * "q5<1>".PIN
+ ce * /"q5<0>".PIN * /"q5<1>".PIN * "q5<2>".PIN
"q5<2>".CLKF = clk ;FCLK/GCK
"q5<2>".RSTF = /clear ;GSR
"q5<2>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9536-15-PC44
T c T T T T T T V T
I l I I I c I I I C I
E k E E E e E E E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
TIE | 7 39 | clear
TIE | 8 38 | TIE
TIE | 9 37 | TIE
GND | 10 36 | TIE
q5<0> | 11 XC9536-15-PC44 35 | TIE
q5<1> | 12 34 | TIE
q5<2> | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | TIE
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
T T T V T G T T T T T
I I I C I N I I I I I
E E E C E D E E E E E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-15-PC44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : OFF
Collapsing pterm limit : 25
Collapsing input limit : 36 |
