Help troubleshooting a JFET circuit.
James Burkart email (remove spam text)
Raising the value of Rs serves to increase negative biasing the gate, which
raises the value of Vds. Lowering it brings Vg closer to 0V, but increases
Id, and increases the voltage drop across Rd.
Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In this case
I do get 15V at Vd since there is virtually no current through the
transistor (spice simulation shows 177pA) but then Vds becomes ~10V.
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On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid <planet.eon.net> wrote: dwayner
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