piclist 2017\09\11\135818a >
Thread: Help troubleshooting a JFET circuit.
www.piclist.com/techref/index.htm?key=help+troubleshooting
BY : Sean Breheny email (remove spam text)

I might be missing something but I don't think this problem is well
designed. I think we can narrow it down to Rs being open but technically it
isn't possible, as far as I can see, to get exactly the voltages mentioned.
Vd=15V implies that absolutely no current is flowing from the supply, so
there shouldn't be ANY voltage drop across the drain-source connection.

Here's my train of thought:

If Rd were open, Vd would be zero.
If Rd were shorted, the current would be limited by the negative Vgs which
would develop (I am defining negative Vgs as Vs>Vg, which reverse biases
the gate junction for an N JFET), so there would be some Vds drop of
several volts.

If Rg were open, I think the FET behavior would tend toward the Vgs=0
behavior where almost the maximum current flows, but then Vd would be less
than 15V.

If Rg were shorted, the circuit would behave almost as if nothing were
wrong, unless 15V was enough to cause reverse breakdown of the gate
junction, but in that case Vd would be less than 15V since an excessive
leakage current would flow.

If Rs were shorted, Vs would be zero.
If Rs is open, then we would expect Vds=0 (Vd=Vs=15). This is the closest
to what we observe. In the real world, the 10Meg input impedance of a
typical multimeter would probably produce something similar to what is
claimed here (it would act as a very high value of Vs) but Vd would not be
identically 15V.

On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid <dwaynerplanet.eon.net>
wrote:

{Quote hidden}

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