piclist 2008\07\21\032728a >
Thread: Eagle ERC questions
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face picon face BY : Xiaofan Chen email (remove spam text)



On Mon, Jul 21, 2008 at 1:07 PM, William Chops Westfield <spam_OUTwestfwspamBeGonespammac.com> wrote:
>
> On Jul 20, 2008, at 6:59 PM, .....kbenSTOPspamspamSTOPspamdca.net wrote:
>
>> Can I do this in Eagle ?  I tried an old v4.15 but, it says I need at
>> least v4.60 to open the schematic.
>
> The short answer is "no."  It is a FAQ and an often-requested feature
> to allow one signal name to have multiple classes (especially analog
> vs digital gnd, and Power vs the short traces to fine-pitch SMT
> pins), but the "one class per signal" bit seems to be very entrenched
> in the design, so it hasn't changed in a long time and doesn't look
> like it's likely that it WILL change in the foreseeable future.

Hmm, do you know any EDA package to allow one net name to
have multiple Net Class associations? As far as I know, Altium P-CAD
does not allow that. Mentor Graphics Expedition Design Capature
does not allow that either.

> The usual fixes involve various sorts of zero-ohm resistors used to
> connect the nets with the same potential but different names, or
> separate routing steps before and after changing the class
> definition,

Last time we tried this with P-CAD and it did not work too well.

> or manual routing,

I believe this is the way to go.

>or living with lots of design rule
> warnings (one thing that IS possible in v5.x is to tell eagle to
> ignore certain warnings.)

We still use the design rules to check the creepage/clearance
between different Net Class. However, manual check is also
necessary. Sometimes we need to get the help from
Mechanical Engineers (inside Pro-Engineer) to check 3-D
distance.

Xiaofan

seeking: why most published
<a276da400807210027u45b6d10av86939dd85fefd6fc@mail.gmail.com> 7bit

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