piclist 2005\08\19\082930a >
Thread: I2C & SPI shared bus
picon face BY : Gerhard Fiedler email (remove spam text)

Olin Lathrop wrote:

>> Then during SPI transfers, there shouldn't be anything that resembles a
>> valid I2C transaction on the bus.
> Huh!!?.  You are practically guaranteed to get some bus start and bus
> stop sequences.  

Since SPI isn't really well-defined WRT data changes vs. clock changes,
this may or may not work. If any of your SPI devices requires you to
configure the SPI master so that there are data changes while the clock is
high or may produce such changes as slave, you are practically guaranteed
to create an IIC start condition while you are sending SPI data.

If OTOH you can guarantee that all SPI data transitions happen while the
clock is low, you can get away with it; in this case there won't be an IIC
start condition during SPI transfers.

I've done it before, and it can work. But it depends on the SPI devices and
their data transition timing.

<128srei64l1uk$.1jz6yewg4xcmi.dlg@40tude.net> 7bit

In reply to: <001b01c5a417$0328dd60$780010ac@radianse.com>
See also: www.piclist.com/techref/i2cs.htm?key=i2c
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Subject (change) I2C & SPI shared bus

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