More TWI problem info
Sean Breheny email (remove spam text)
I have a bit more info on the problem I'm having with using TWI on an
I have two ATmega128s talking via TWI. One is always master, the other
always slave. There are no other devices on the bus.
The master occasionally "locks up". It does so right after you command a
stop condition after completing a master receive operation. When I say
"locks up" I do not mean that the process stops running code (it is still
running code) but rather that the TWI interface seems to stop working.
That is, it never finishes the stop command (the TWSTO bit stays high and
the SDA line stays low). This happens even without the slave connected
(so the slave is not the one pulling the SDA line low).
Also strange is that I have a JTAG ICE and when
I use it to debug the problem, the following happens:
I have a loop after I command the STOP operation where I wait for the
TWSTO bit to go low (indicating that the STOP operation is completed).
When I use the ICE to break the processor during the TWI malfunction, and
then inspect the TWCR, I see that TWSTO is set and TWWC is clear. If I
then single step once, the TWWC bit goes high. I have a breakpoint on my
TWI interrupt routine so I can make sure that no TWI interrupt happens
during that single step and it doesn't, so there should be no part of my
code that could be writing to the TWDR during that step, which, as I
understand, is the only way that TWWC should be able to go from clear to set.
Any ideas? I've spent the whole day on this and I'm beginning to get
desperate :-) My next step is to try another board in case there is a
hardware problem. Luckily, I have another board to try.
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