AC mains into PIC pin
Russell McMahon email (remove spam text)
> Well, based on what you and Roman have input here the following would
> work for 240VAC (assuming shitty Australia and New Zealand power);
> * Two resistors in series - say 3~4M each
> * 5.1V Zener from Pin to GND - only small wattage, I assume is OK
> * up to say 100nF Metalised cap (rated at 400V) strapped across Zener
> * a pair of Schottky diodes on input pin
Yes-ish, for positive input.
Need to check leakage specs, zener bias point and time constants as Olin
Transient behaviour would need to be verified (and found wanting :-) ).
Add second zener to supply (suitable polarity) for negative input.
(Otherwise its just a poor diode (about 0.8v maybe) and you have no negative
Even 5v1 violates spec but can be thought about. (ie it would work :-) ).
> How do you feel about sinking the gate current to a PIC pin through a
> single resistor - if maintained at around 5mA?
I feel very positive about it.
I'm absolutely CERTAIN that it would cause undefined and undefinable
operational problems in some cases.
As a PROTECTIVE system where the CPU was meant to live but not be
guaranteed to be able to chew gum during OR AFTER mains application it's
fine. CPU would need to be powered down (to under 0.1V on Vdd*) and
restarted after the event to be certain operation would be OK. Resistor
would need to be AT LEAST 2w rated at 5 mA. Resistor would need to be X
rated (a la caps spec) - most small resistors do NOT have suitable voltage
ratings for off mains use, regardless of power dissipated. Transients would
need to be considered separately.
* Based on experience.
Once latchup occurs it can remain until Vdd falls to a very low level. My
experience is that < 0.1V on Vdd removes non-destructive latchup but
voltages above this may not. In many systems Vdd falls to under about 0.5V
rapidly due to junction conduction but then falls much more slowly due to
resistive only loads. The latchup state MAY remain for tens of seconds.
Antibrownout and reset will not cure this.
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