piclist 2002\10\20\034555a >
Thread: Sizing fans for MOSFETs
face BY : Russell McMahon email (remove spam text)

> I am in the process of designing some motor controllers  and am thinking
> removing (or at least reducing the size of) the heatsinks I am using by
> placing a fan over the MOSFETs.  I have some datasheets from Wakefield
> Engineering the nicely show the Thermal Resistance from Sink to Ambient
> different LFM rates.  From this I have been able to determine I could get
> away with a very small  heatsink.  What I can not determine is if I need a
> heatsink at all.  Does anyone know where I can find a Thermal Resistance
> from Sink to Ambient for different LFM rates for a TO-220AB casing (i.e.
> with no heatsink)?  Does it sound reasonable that with an ~500LFM fan I
> could put 30A through an h-bridge that consisted of 2 IRF1404 MOSFETs
> on resistance) in parallel for each leg?

I'd say just about yes :-)
Nice FETs!

It's not obvious why you are placing two FETs in parallel per leg. The
IRF1404 is rated at 162A (junction) and 75A package.
AT Rthj-c-max of 0.75C./W and Rcase-sink-typ of 0.5C/W you only get about
1.25 C/W rise and at 4 times the power dissipation below (due to one FET
being used per leg rather than 2) this would still allow lots of room for
heatsinking. I would have thought that the space and cost saved by halving
the FET count would allow extra heatsink room for forced cooling.

Ifet = 15A (2 FETS)
Rdson = 4 mohm
Duty cycle = 100% say (worst case just in case)
P/Fet = I^2R = 225 x .004 = 900 mW/FET
A vertically mounted TO220 package will about handle that without any
assistance at all and I imagine a substantial airflow onto the metal of the
package or, more realistically, using a minimal heatsink of about equivalent
area to the face of the package, would allow fan cooling. It depends of
course what you meant by "no heatsink" - the exposed face of the package
when mounted has a higher and unspecified thermal resistance (the 62 degrees
C /watt refers to the whole package). . It you had access to the back faces
or clamped a row of close spaced FETS (8 total here) to a piece of metal not
bigger than the FETS themselves and force cooled that you would effectively
have no heatsink. Standing them up in a forced draft would have the same

The great risk is that that utterly fantastic Rdson degrades for any reason
or if you get other energy dissipation contributions !!!!!!!!!

You don't say what the application and switching speed is, and this can
greatly influence decisions here.
You would have to ensure that the FET was fully enhanced and that
dissipation due to switching transitions were well managed. I suspect that
dissipations several times as much as the 900 mW per FET may occur in
practice.  If load sharing between the two FETs per leg became imbalanced
the power dissipation could increase dramatically. eg for a 2A mismatch the
current goes from 15/15 to 17/13 and power in the 17A FET goes to 1.2W (25%

       Russell McMahon

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