[EE]: Flip-Flop with memory
Mike Hardwick email (remove spam text)
Here's a concept: Connect a capacitor at the D input of a D type FF. Charge
the cap through a large resistor, so that it takes a second or two to
discharge after power is cut. Clock the FF once at power-up time,
immediately after supply voltage stabilizes. The Q output gives your
desired status after power up. If the cap gets discharged by leakage
through the D input when your supply is at zero volts, isolate it with
>I need a flip flop circuit with a one or two second memory
>after power has been removed and then turned back on.
>12 Vdc level to power two different circuits through transistors.
>It has to work like this :
>1. power applied / output 1 active
>2. power removed & re-applied before timeout / output 2 active
>3. power removed & re-applied after timeout / output 1 active
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