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Thread: 24Bit Up/Down Counter at 40 MHz
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face BY : James Lee Williams email (remove spam text)



My PIC processors will be running at a full 20MHz.  Both SRAMS are to
have there own address generators, however I do not want the pics to
generate the actual address.  What I want the pics to do is just inform
the address generator logic to either increment the address point,
decrement it or reset it.  PICa will not be writing to the same bank as
PICb will be reading from, hence the reason for separate buses for the
RAM.  The reason for this, is that I must have as fast as possible
access to large amount of buffer ram.  This is for fast rastering motion
with a laser cutting system.  I'm talking in the order of 100 inch per
second * pixel resolution perfermance.

Regards,

James


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Subject (change) 24Bit Up/Down Counter at 40 MHz

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