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Thread: 24Bit Up/Down Counter at 40 MHz
face BY : James Lee Williams email (remove spam text)


I am trying to implement a 512Kbyte external buffer using a 8bit
parrallel memory device.  However, I want to be able to control only the
following for addressing the bytes in the RAM.
1.  Clear Address Counter
2.  Increment Address Counter
3.  Decrement Address Counter

I want to use only these three signals coming from a pic to control the
addressing to the ram.  However, I can seem to find any counters with
this number of address lines.  Does anyone have any suggestions for
tackling this.  The reason for this, is that I want to be able to read
data from the ram in not more that 3 instruction cycles.

Also, maybe someone can also give me some suggestions on how to have
this ram accessable from two different pic devices.  One pic will only
write to the ram, while the other pic will only read from the ram.
However, I will in reality have to of these 512Kbyte chips, configured
in such a way that one pic can write to RAM of chip 1 while, at the same
time the other Pic will be able to read from chip 2.  The trick here is
that the the data buses much be able to be released from each Pic or
inserted.  But never both Pics at the same time.  I have been thinking
about using a dual bus transciever for each RAM chip.  Then use hardware
logic to prevent simaltaneous access to the same chip by both
controllers.  If anyone any clever ideas on this or comments, you input
would be greately appreciated.



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Subject (change) 24Bit Up/Down Counter at 40 MHz

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