PWM glitch-free updates
Mike Mansheim email (remove spam text)
> What's the best strategy for dealing with updating
> a 10-bit PWM value asynchronously with TMR2?
> It looks like you could get a glitch if the update
> happens to occur just as TMR2 is overflowing.
quote from the F87x data sheet:
"The CCPR1H register and a 2-bit internal latch are used to double buffer
the PWM duty cycle. This double buffering is essential for glitchless
and (earlier in the discussion):
"...but the duty cycle value is not latched into CCPR1H until after a
match between PR2 and TMR2 occurs..."
From the comments by Spehro & Olin, is this all hooey??
(by the way, my applications of pwm typically wouldn't care about an
occasional glitch, but now I'm curious)
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