Mike Mansheim email (remove spam text)
>my question is befor and after pulling SDA low where the SCL was ?
Master drives SCL low after 8th clock pulse; has to remain low for
specified time (4.7 us? don't remember). Just after driving SCL
low, master releases SDA (makes it an input) so device can control
it. If the device is going to ack, it has to drive SDA low while
SCL is low. Master executes 9th clock pulse; looks at SDA during
the pulse (i.e. while SCL is high). If SDA is low, then it has
received the ack.
If the device knows that it is not going to have enough time to
decide if an ack is appropriate, then it can hold SCL down until
it is ready to either drive SDA down or release it high. This is
clock stretching - when the master releases SCL high for the 9th
clock pulse, it needs to wait until SCL has actually gone high,
which will happen when the device releases SCL.
One of the things that makes this bus work is that any device can
drive (or hold) SCL and SDA down.
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