F876 programming questions
Tony Nixon email (remove spam text)
Mike Mansheim wrote:
> The progamming spec says that programming mode is entered while holding
> RB6 & 7 low while raising MCLR from Vil to Vihh (which needs to happen
> within 72 osc clocks). Vil is defined in the F876 data sheet as the
> "input low" voltage; essentially ground. However, when watching the
> promate operate on a scope (working with the micro in-circuit), MCLR
> and Vdd come up together to 3-5V for 10's of milliseconds, then MCLR is
> bumped to 13V to go into programming mode. So I'm wondering what exactly
> the requirements are to enter programming mode. Can a "running" chip
> enter programming mode just by having MCLR raised? If so, what are the
> 72 osc clocks relative to?
I activate VCC then a few 10's of millisecs later raise MCLR from ground
to ~13V. That's all you need to do. The 72 osc clocks will relate to the
reset feature in the chip. The OSC1 pin should be tied low (or high),
and not left floating, before and during the programming process to stop
any clock pulses incrementing the program counter.
> Regarding the "read data" command, the timing diagram shows that the data
> line is an output for the last 15 bits of the data string. However, when
> I do this, I always show the last bit being a "1", when the data string is
> supposed to be "0", data(14), "0". Is this ok? Or should I revert for the
> last bit and assert the "0"?
> Sorry for the long post, and thanks for any help.
That sounds about right.
RB7 goes to an output after the 2nd rising edge of the clk. It then goes
to HiZ after the 16th rising edge, which will leave RB7 floating. You
may then read a 1 or a 0. It doesn't matter anyway because this data bit
is not used.
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