piclist 2001\01\11\055848a >
Thread: Looking for modified UART virtual peripheral (parity bit/parity decode, framing error detect)
picon face BY : Russell McMahon email (remove spam text)

>I am using an SX28 microcontroller, including the UART virtual peripheral.
If someone has modified the VP
>to detect and decode a 9th parity bit and framing error, I would appreciate
the forwarded source code.
>I am sure its easy to do, yet if someone has proven source code, it would
save me time.


I haven't done this yet but I would be interesting in exchanging notes
offlist (or on if useful).
I am using an SX28 with triple VP UARTS based on their dual UART plus
Multimaster IIC plus timer example.

I believe their sample code for the dual UART implementation has a sometimes
but not always fatal bug. This bug does NOT apply to the single UART version
but is a product of incorrectly expanding it to a multi-UART clone. As I
understand the code you could use either UART OK and both at once maybe. I
have corrected this and my version works but the original problem was
combined with a hardware fault so I never saw how well their version
actually worked in practice. I suspect that in many cases the fault would
not have been obvious.

I don't need the 9th bit at this stage but thought it may be useful to mimic
the Philips extra bit they use for flagging addresses in a multi processor
coms system.

Outline suggestions and thoughts:

The VP UARTs TX routine actually uses 2 data bytes and should handle up to
16 bits (including all starts and stops and parities) so should be easily
modified. This is a strangely inefficient use of registers but makes your
requirement easy.

At present txlow contains only a start bit in bit 7. Data proper is in

                   rr      tx_high   ; and shift to next bit
                   rr      tx_low   ;
                  dec     tx_count  ;decrement bit counter
                  snb tx_low.6  ;output next bit

By packing the bits differently

       Start bit in txlow b6
       Data in Txhigh 6 to txlow 7
       Parity in tx high 7

And changing the snb tx_low.6 above to snb tx_low,5 the code will send 1
start bit, 8 data bits, 1 parity.
(This is outline only - other code will need changing including sb tx_low.6
a few lines down).

Unfortunately, the RX routine only uses a single register for the data byte
so you will probably have to add extra code to detect the occurrence of the
9th bit and save it separately.

     dec     rx_count                ;last bit?
     sz                              ;if not
     rr      rx_byte                 ; then save bit
     snz                             ;if so,

At present this just fills rx_byte with the 8 bit data word.
By increasing the initial value of rx_count by one this will cause the lsb
of data to overflow into carry when the above code completes.
By reading carry immediately after this you can recover the last data bit
and the parity bit is contained in rx_byte.7

Use above ideas with care. YMWV !!! :-)



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Subject (change) Looking for modified UART virtual peripheral (parity bit/parity decode, framing error detect)

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