Drew Vassallo email (remove spam text)
>> btfsc TMR0,7 ;Check for timer hitting zero
>> goto Comm_Bit_Loop ;If not, then keep looping
>> bsf TMR0,7
I guess I don't understand this, since even if you clear the TMR0 register
before entering this loop, it will show "zero overflow" according to the bit
7 test when TMR0 gets to 128, not 256. I NEVER use bit 7 for a 'pass zero'
test unless you're using decf or otherwise subtracting a value less than
>I guess that works, but it's not really what I had in mind.
I don't see how it could work.
>Is it true that the int flag is set, even when not enabled?
>Figure 6-1 and 6-6 show no dependencies between the timer register and the
I've used the T0IF bit to detect TMR0 overflow without enabling the
interrupt and it works fine. Yes, the datasheet is correct in stating that
the flag bit is set regardless of the mask.
Are you using the watch window to monitor the INTCON register for the T0IF
bit? If so, what does it do when TMR0 overflows? Note that it doesn't get
RESET - you have to clear the flag bit in software after it's set by TMR0
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