piclist 2001\01\02\115416a >
Thread: Picky I/O
face BY : David VanHorn email (remove spam text)

>>Umm..I don't think that statement is entirely accurate.  When the pin is
>>switched to an output (by modifying the TRIS register), whatever is in the
>>the port latch is output on the pin.  The critical point is that you cannot
>>guarantee what is in the output latch if you have performed ANY Read Modify
>>Write operations on the port latch since that pin was configured as an
>>input.  The only safe ways this can be done is to either set the output
>Of course you're right.  I think I omitted that critical piece of
>information in my haste to make it brief.  I believe, though, that I
>included this information later on in my message.  Sorry for the confusion.

The key issue on read/mod/write with port registers, is that there is
external hardware that may drag pins to different states than is currently
in the port register.  IF you can determine that this is not a problem,
then there should be no problem with using these instructions.  In my case,
with a 0.1uF cap through a 1k, I know that this pin will be heavily loaded,
but I'm not doing anything else on the port when it matters, and when I am
doing other things on the port, the state of this pin is irrelevant.

I haven't tested these instructions exhaustively with internal registers
(like tris) but I believe that it's not a problem, as long as you avoid
sequential ops to the same port. That's easy enough, through re-arrainging,
or nops.

It is a nasty-ism in the pics though.
In the AVR, this just dosen't happen. You have port, pin, and
tris-equivalent registers, where port is the output, and pin is the input
(causes newbieations!)
Bit set and reset is free of any constraints on sequential operations as well.

Where's dave? http://www.findu.com/cgi-bin/find.cgi?kc6ete-9

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