piclist 2001\01\02\104554a >
Thread: Picky I/O
face BY : David VanHorn email (remove spam text)

>Umm..I don't think that statement is entirely accurate.  When the pin is
>switched to an output (by modifying the TRIS register), whatever is in the
>the port latch is output on the pin.  The critical point is that you cannot
>guarantee what is in the output latch if you have performed ANY Read Modify
>Write operations on the port latch since that pin was configured as an
>input.  The only safe ways this can be done is to either set the output
>latch once and never do any RMW operation on that port, which is a tad
>limiting, or explicitly set the the port latch every time before you clear
>the TRIS bit.

At this point, I'm ok.
I'm able to do BCF and BSF on the tris register, and on the port with
predictable results.

I had a couple problems hitting me at the same time, giving some pretty
wierd symptoms.

One point of note, I had missed that RA4 is open-drain, and therefore can't
drive high no matter WHAT you do in the code :)

Where's dave? http://www.findu.com/cgi-bin/find.cgi?kc6ete-9

http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads


In reply to: <0F60BEDDC090D41185D300508BCFA39E0AF960@zpgty002.europe.nor tel.com>
See also: www.piclist.com/techref/microchip/ios.htm?key=i%2Fo
Reply You must be a member of the piclist mailing list (not only a www.piclist.com member) to post to the piclist. This form requires JavaScript and a browser/email client that can handle form mailto: posts.
Subject (change) Picky I/O

month overview.

new search...