Bug in LTC2400 SPI interface
Dan Michaels email (remove spam text)
Morgan Olsson wrote:
>The error occours when using the polled mode, i.e activating the CS (Chip
Select) to read the EOC flag (End Of Conversion) that LTC2400 then as
response outputs in the SDO pin, then if it is ready we read out the result,
if it is not we deactivate CS and later test again.
>It then, very rarely, and not in all implemetations, happen, that the 32
bit data comes in one bit too early. Very funny, eh?
I am not sure this pertains to what you are seeing, but the LTC1400/1404 chips
have the following constraint on CS and Sclk timing:
"If the time from CONV signal to CLK rising edge is less than
t2, the digital output will be delayed by one clock cycle".
t2 is spec'ed at 80 nsec minimum - should not be a problem with a PIC, even
running 20 Mhz.
There are also some constraints on how long the CS pulse can be - as
related to accuracy of the final result.
- Dan Michaels
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