piclist 2000\06\05\192312a >
Thread: External SRAM on PIC (or AVR)
picon face BY : Tony Nixon email (remove spam text)

Bob Ammerman wrote:
> Yep, the external RAM chip with a counter for address input makes a lot of
> sense. I designed, but never implemented a scheme that would have the
> following characteristics:

I used this approach to aquire data from a PIC 74 at 10K samples and
store to a 128K RAM chip with inbuilt battery backup. (Dallas)

If you are using DIP RAM chips you can mount the address decoder
directly under the chip to save space. 10 pins to the PIC (8 for data),
but limitation is sequential read/write. Add a parallel to serial chip,
and probably 4 PIC pins used.

The track layout can be simplified because all the Q outputs from the
binary counter chip can be connected in any order to any of the RAM
address pins. The data will still read in or out the same for any given
address. Using this approach I just fanned out the address leads to the
nearest RAM pin.

Best regards



<393C35AE.3D173736@eng.monash.edu.au> 7BIT

See also: www.piclist.com/techref/microchip/memory.htm?key=sram
Reply You must be a member of the piclist mailing list (not only a www.piclist.com member) to post to the piclist. This form requires JavaScript and a browser/email client that can handle form mailto: posts.
Subject (change) External SRAM on PIC (or AVR)

month overview.

new search...