piclist 2000\06\05\191037a >
Thread: Re: Phase of internal TMR0 clocking
picon face BY : Tony Nixon email (remove spam text)

Dmitry Kiryashov wrote:
> Hi Tony.
> Can you explain what do you mean getting back in sync with internal clock ?
> Situation is following: prescaler=1, internal osc/4 is used.
> WBR Dmitry.
> > > > Another question: I still can't understand what was the real reason to introduce
> > > > 2 clocks delay in TMR0 increment after loading TMR0 with new value.
> > > I don't know either. I suspect that there's some kind of pipeline thing that has
> > > to get flushed and updated, but that's just a guess
> > To me it looks like the SYNC circuit takes two cycles to get back in
> > sync with the internal clock after writing to TMR0. (Another guess)

If you look at the data sheet and the TMR0 block diagram, you will see a
SYNC circuit following the PSA MUX. The data sheet mentions a (2 cycle
delay) under the SYNC block. Whether this is coincidence or related, I
don't know.

Best regards



<393C3352.B1B6131A@eng.monash.edu.au> 7BIT

See also: www.piclist.com/techref/microchip/time.htm?key=clock
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Subject (change) Re: Phase of internal TMR0 clocking

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