piclist 2000\06\05\190822a >
Thread: External SRAM on PIC (or AVR)
face BY : Dan Michaels email (remove spam text)

Bob Ammerman wrote:
>Yep, the external RAM chip with a counter for address input makes a lot of
>sense. I designed, but never implemented a scheme that would have the
>following characteristics:
>1: 12 I/O's (or maybe 11? if I recall correctly) required for access
>2: easily adaptable to 2^16=64KB, 2^20=1MB, 2^24=16MB or more  bytes of RAM
>3: '161 counter chips for address inputs
>4: Random access time on the order of about 10-20 PIC instruction cycles.
>5: Sequential read access time on the order of about 3 PIC instruction
>cycles (bsf CLOCKBIT, bcf CLOCKBIT, movf DATAREG,W).
>6: Sequential write access time on the order of about 5 PIC instruction
>cycles (movwf DATAREG, bsf CLOCKBIT, bcf WRITEBIT, bsf WRITEBIT, bcf

I have a 20Mhz SRAM board I designed/had built [but still sitting in the
box], which uses 4 74AC161 chips + logic, but this is rather bulky for
a little PIC embedded system. So, I looked at putting the counter/logic
in a PAL, but here it even takes 2 24-pin chips AFAICT.

>By the way, we can kind of tie this thread to the 'PIC on Internet' thread.
>A reasonable amount of SRAM, even if non-sequential access is rather
>inefficient, would go a long way to implementing a decent protocol stack.

Would this stack require extra code space, or just data RAM?

>It seems reasonable, but I sure would like to find the logic all wrapped up
>in one chip. I even considered something like the XILINX chips, but too many
>$$ for chips and especially for tools.

Ha, in my neighborhood that's what you call a 40-pin PIC. Seems a waste
of a nice little PICy just to access address/data/control lines, but it
does unfortunately take all the available lines on the PIC - but then you
also have RS-232/I2C/custom s.w./etc capability. Try that on XILINX.

best regards,
- Dan Michaels
Oricom Technologies


See also: www.piclist.com/techref/microchip/memory.htm?key=sram
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