piclist 2000\06\05\184331a >
Thread: External SRAM on PIC (or AVR)
www.piclist.com/techref/microchip/memory.htm?key=sram
picon face BY : Bob Ammerman email (remove spam text)



Yep, the external RAM chip with a counter for address input makes a lot of
sense. I designed, but never implemented a scheme that would have the
following characteristics:

1: 12 I/O's (or maybe 11? if I recall correctly) required for access
2: easily adaptable to 2^16=64KB, 2^20=1MB, 2^24=16MB or more  bytes of RAM
maximum
3: '161 counter chips for address inputs
4: Random access time on the order of about 10-20 PIC instruction cycles.
5: Sequential read access time on the order of about 3 PIC instruction
cycles (bsf CLOCKBIT, bcf CLOCKBIT, movf DATAREG,W).
6: Sequential write access time on the order of about 5 PIC instruction
cycles (movwf DATAREG, bsf CLOCKBIT, bcf WRITEBIT, bsf WRITEBIT, bcf
CLOCKBIT)

By the way, we can kind of tie this thread to the 'PIC on Internet' thread.
A reasonable amount of SRAM, even if non-sequential access is rather
inefficient, would go a long way to implementing a decent protocol stack.

It seems reasonable, but I sure would like to find the logic all wrapped up
in one chip. I even considered something like the XILINX chips, but too many
$$ for chips and especially for tools.

Bob Ammerman
RAm Systems
(high function, high performance, low-level software)
[and occasionally hardware, if it's digital  :-)]

{Original Message removed}
<020a01bfcf3f$61e74920$269b9cd1@ramdell> 7bit

See also: www.piclist.com/techref/microchip/memory.htm?key=sram
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