piclist 1999\10\19\214301a >
Thread: Serial I\O (was Re: TMR0 Latency]
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picon face BY : Thomas Brandon email (remove spam text)



Yep, this and the hardware context saves for interrupts make the Scenix a
dream for this task. Having 10X more instructions doesn't make it any harder
either. Also, the versatile port configuration helps. On the PIC I could
only have interrupt on change (actually, I wasn't going to use this as the
time to determine interrupt source was a problem, better done through my own
polling) whereas I can have selectable edge sensing on all the Port B pins
on a Scenix. Yep, the scenix is the way to go for this. I have ordered the
Parallax SX Tech Kit to this end.

The application is MIDI which is 31250bps. I will prob. either run 16X (100
inst\bit) or 8X clock as in hardware UARTs (16X) and simply sample at the
middle of each bit. This will increase the number of interrupts but decrease
the ammount of logic in the timer interupt. There should be no problems
implementing 8 channels of I\O in terms of speed, the only trouble would be
you could only manage 8byte buffers for each channel, and that would only
leave 8bytes RAM left. This just means I have to rid of the data quickly.
Also, by having non fixed FIFO's I could dramatically limit the number of
overflows. It's unlikely all channels will be active at once so a shared
FIFO is prob. better (need extra 3 bits per message tho., or runtime stack
style partitioning).

I have one problem with MIDI I\O tho. How does 1 stop bit work in terms of
synchronising to it? In a modem the RTS\CTS can be used to stop data flow to
sync. to the next start bit. But MIDI has no hardware flow control. So If a
device is only giving 1bit (exactly) stop bits, how can you determine what's
a start bit? You have no way of knowing if it's a stop bit or a data bit.
Does anyone know how to get around this or is it not really an issue in
practice.

The other thing I was wondering was does anything reset the prescaler count
of the timers? I gather the prescaler is just a bunch of flip flops
selectively enabled based on the prescaler. Under what circumstances does
this reset? For instance, if a TMR0 (RTCC) overflow interrupt occurs with
say a 16:1 prescaler, you take say 5inst to find it's a TMR0 overflow and
then you update TMR0 to give the appropriate delay, it is still 5 (6 now)
instructions into the 16 cycle count is it not.

Tom.
----- Original Message -----
From: Stephen Holland <stephen.holland@spam@spamUSA.NET>
To: <PICLISTRemoveMEspamMITVMA.MIT.EDU>
Sent: Wednesday, October 20, 1999 7:36 AM
Subject: Re: [Re: TMR0 Latency]


The Scenix SX has jitter-free response to internal and external interrupts,
and also takes care of the context saves. Just 3 cycle interrupt response
and
3 cycle return from interrupt, both are deterministic.

What serial rate do you need?

Stephen

<015301bf1a9c$d66d4950$fb255e81@tb> 7bit

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