piclist 1999\10\18\195305a >
Thread: TMR0 Latency
face BY : Dennis Plunkett email (remove spam text)

At 09:31 19/10/99 +1000, you wrote:
{Quote hidden}

This may sound crazy for a PIC but is common code practice in a DSP type
aplication, e.g. G728 to G711 conversion where processing is performed in
blocks, but data is input and output on an 8kHz cycle

{Quote hidden}

Yeh go there.
You say that timing is critical, well maybe, but it is realy only is on
receive, which is asynchronus and all transmit may be sychronus to each
other. The main problem is the speed of the incomming data. Sampling at 3
times the expected incomming data rate will remove the need to trigger an
interrupt and line up the receiver, however the second method uses less
processing power as you can then start sampling in the expected middle of
the data stream etc.

Whatever, enjoy



See also: www.piclist.com/techref/index.htm?key=tmr0+latency
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