piclist 1999\10\18\192731a >
Thread: TMR0 Latency
picon face BY : Thomas Brandon email (remove spam text)

---- Original Message -----
From: Paul B. Webster VK2BZC <paulbspamspamMIDCOAST.COM.AU>
To: <spamPICLISTspamBeGonespamMITVMA.MIT.EDU>
Sent: Monday, October 18, 1999 11:17 PM
Subject: Re: TMR0 Latency

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That's purposeful, there's too much to do in the given time to waste 6inst.
saving context, everything would happen in the TMR0 interrupt to prevent
context saves, sorry for not making clear.

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Not so much interrupts, just PIC interrupts. Scenix interrupts with
"determnistic jitter free 60ns int., 100ns ext" interrupts with hardware
context saves would be much more acceptable.

> > Is there any jitter in the internal interrupt handling?
>   Yes, depends on whether it happens to hit a branch instruction.
That could be a problem. I don't need to do anything in the main code, but
to infinitely loop I need lots of jumps (well, just one, but it's executed a
lot), so there would be a lot of 2 cycle inst.'s.

{Quote hidden}

The application is multi channel serial comms. As such, the task must be run
with accurate timing but there is a lot to do in the given loop time and the
amount of processing varies dramatically (a lot of the time the loop will do
nothing as no serial lines are active). Hence, the time taken to calculate a
variable delay and implement it is a big problem.

Anyway, as suggested above, the scenix's interupts and speed are much more
suited to this task so I believe I will switch.


<005401bf19c0$dc61dec0$fb255e81@tb> 7bit

See also: www.piclist.com/techref/index.htm?key=tmr0+latency
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