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Thread: TMR0 Latency
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picon face BY : Thomas Brandon email (remove spam text)



I am looking at a project requiring a very tight timing loop. Ideally I
would have it accurate to a single instruction but maybe 1 instruction error
could be tolerated. What delays are present in a TMR0 interrupt on overflow
driven loop. The basic idea would be (assuming TMR0 overflow is the only
enabled interrupt):
delay EQU ...
int_latency EQU ...

ORG 0x004
   MOVF delay
   SUBLW int_latency
   MOVWF TMR0

where delay is the number of cycles (if prescaler = 1:1) and int_latency is
the total latency of the interrupt occuring and of setting TMR0. In this
case int_latency would be 3 inst (MOVF-MOVWF) + the delay for the interupt
to fire + the delay for the setting of TMR0. From reading the MChip docs I
think that there is a 4 inst delay for the interrupt to fire and actually
execute 0x004 for real, and a 2 inst delay for the update of TMR0 to kick
in. Hence I would set int_latency to 4 + 2 + 3 = 9inst. Is this correct? Is
there any jitter in the internal interrupt handling?

<00f901bf190e$a924c8e0$fb255e81@tb> 7bit

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