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Thread: Nested Interrupt questions
www.piclist.com/techref/microchip/ints.htm?key=interrupt
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picon face BY : Thomas Brandon email (remove spam text)



Has anyone written a program that dealt with interrupts occuring during an
interrupt. I know there are no nested interupts but from reading the docs,
the following 2 methods should allow (some) interupts during interrupts to
not be missed (delayed, but not missed):
1) Process interrupt as normal. Clear bit of specific interrupt dealt with.
Copy the PIR registers to memory and then clear them. In code after
interrupt, check saved register and deal with any other interupts. The
pseudocode would then be something like this:

Interrupt Handler:
   Find interrupt cause
   Handle interrupt (1)
   Clear appropriate bit
   Copy PIR's to memory (2)
   Return From interrupt (3)

Any interrupts between (1) and (2) would set the appropriate PIR bit , but
as the GPIE is clear no interrupt will occur. Any interrupts occuring
between (2) and (3) will trigger after (3) due to the GPIE being set again
via RETFIE. The only problem is if this occurs what do you do with the
interupts saved at (2) but not yet dealt with. You could deal with this at
the beginning of the interrupt handler but this could considerably lengthen
the interupt processing time.

This is really only suitable when all processing is interrupt triggered. The
background loop would simply continually check the appropriate memory for
missed interrupts. This is about all this loop could do assuming reasonable
interrupt response is needed.

2) Simply ignore the fact that multiple interrupts can occur. Do priority
interrupt handling (i.e. deal with only one interrupt at a time) and only
clear the appropriate bit. Thus when RETFIE is called and GPIE is set any
pending interrupts will trigger.

The 2nd method is slightly more flexible in that background processing can
continue however it means interrupts will be delayed by other interrupts.
After calling RETFIE there will be an approx. 3TCY delay to the next
interrupt trigger. Hence if 3 interrupts occur at once there will be 6TCY
and the processing time of the other 2 interrupts delay. Also, to ensure
adequate handling of critical interrupts, priority checking must be done
adding further processing time.

Both of these methods could be improved by simultaneously handling multiple
interrupts where appropriate but again extra logic is required.

Has anyone implemented an interrupt critical system on a PIC? How did you
get around the problem of overlapping interrupts? Are there any problems in
the above methods?

Tom.

<04b501bf144d$23654560$fb255e81@tb> 7bit

See also: www.piclist.com/techref/microchip/ints.htm?key=interrupt
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