Philips TV/VCR PLL @ low Fosc anyone ?
Peter L. Peres email (remove spam text)
has anyone tried to run a Philips TV/VCR synthesizer chip at a lower
Fosc than specified to obtain lower channel spacing (as required for HF
and other apps) ?
Are there implications on the I2C timing due to this ?
See also: www.piclist.com/techref/logic/dsps.htm?key=pll
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