piclist 1998\11\03\125409a >
Thread: shift registers
picon face BY : Peter L. Peres email (remove spam text)

On Mon, 2 Nov 1998, John Payson wrote:

> The difficulty comes when, e.g., the clock is fed to shifters on
> two separate boards and it's slope-limitted to minimize EMI.

Actually the trick with slow CMOS-B D flipflops is, that if the slope on
the clock is reasonably fast it is guaranteed that the next stage will
latch properly. The reason is the output buffer of the previous stage that
adds a natural 'two inverter' delay. This can be in the order of 200nsec -
1usec for CMOS-B series at 5V. So, all you have to do is, give them clock
with a flank better than 200 nsec. This is why I often use a 40106 to
boost the clock signal on an extender board when it was slowed down for
RFI suppression purposes. The PIC and other micro-controllers all have
flanks that are very fast vs. CMOS speed, and never cause problems in this



In reply to: <01BE067C.6D5D8770@JOHN_WKST1>
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