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'stopped crystal'
1997\07\11@092850 by Mal Goris

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Does the CLKIN pin really have to be taken to 0 volts during ISP
programming? Or can it just be left attached to the crystal?

Mal Goris
--
http://www.nfra.nl/~mgoris/

1997\07\11@105908 by John Payson

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> Does the CLKIN pin really have to be taken to 0 volts during ISP
> programming? Or can it just be left attached to the crystal?

If the CPU is allowed to execute any instructions between /MClr's rise to
"+5" and its rise to "+13.5" [or more accurately, between 4v and 8v] then
programming will start not at zero, but at the instruction after the last
one executed.  This will usually corrupt programming (often causing the
system to behave quite wierdly).

There are three ways to avoid this problem: [1] Keep CLKIN frozen while prog-
ramming is started.  If CLKIN isn't running, the chip won't execute any
instructions.  [2] Use circuitry which can pull /MClr *quickly* from VSS to
VPP (too fast for the CPU to start executing anything).  If you're using
RC clock mode, I wouldn't count on this latter method working, but if you're
using a crystal the "oscillator start timer" should help you out.  [3] If
you're using RC mode on a 16x84, you could enter programming mode, burn the
config fuse for another oscillator type, then reset, program the part, and
finally reburn the config for RC.

Note that a pre-burned 12C5xx may not have an oscillator input, nor a /MClr
reset.  On these chips it's necessary to ensure that /MClr's rise happens
very soon after application of VDD.

1997\07\11@142816 by www.aeug.org/~chip/

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On Fri, 11 Jul 1997, John Payson wrote:

> > Does the CLKIN pin really have to be taken to 0 volts during ISP
> > programming? Or can it just be left attached to the crystal?
>
> If the CPU is allowed to execute any instructions between /MClr's rise to
> "+5" and its rise to "+13.5" [or more accurately, between 4v and 8v] then
> programming will start not at zero, but at the instruction after the last
> one executed.  This will usually corrupt programming (often causing the
> system to behave quite wierdly).

 An additional question: can CLKIN's level be allowed to toggle up and
down *after* programming/test mode is entered?

 --Scott

/**/

1997\07\11@151212 by John Payson

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>   An additional question: can CLKIN's level be allowed to toggle up and
> down *after* programming/test mode is entered?

Experience shows that the oscillator is disabled when /MCLR=VPP.  I think
it likely that other code-execution tasks are disabled as well though I
may be mistaken.  Are you using an externally-clocked CPU?

1997\07\11@170230 by Andy Kunz

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At 01:53 PM 7/11/97 -0500, you wrote:
>>   An additional question: can CLKIN's level be allowed to toggle up and
>> down *after* programming/test mode is entered?
>
>Experience shows that the oscillator is disabled when /MCLR=VPP.  I think
>it likely that other code-execution tasks are disabled as well though I
>may be mistaken.  Are you using an externally-clocked CPU?

That is true so long as the rise from .8Vdd to Vpp does not take so long
that the oscillator starts running.  If it starts running, then the PC will
be off by the number of cycles/4 that occurred.

Don't ask how I learned that bugaboo!

Andy

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