Searching \ for 'power off' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/power.htm?key=power
Search entire site for: 'power off'.

Truncated match.
PICList Thread
'power off'
1997\03\10@134215 by Shawn Ellis

flavicon
face
Hey, all, I know this was already a discussion, but it was never answered
to my satisfaction...  I have a PIC based card here that doesn't go
absolutely to 0 VDC when power is off... the PIC always screws up...  Can
someone PLEASE suggest a simple-reliable solution?  Can microchip put a
GND-shorting switch in their parts?

1997\03\10@140611 by Mike

flavicon
face
At 01:38 PM 10/03/97 -0500, you wrote:
>Hey, all, I know this was already a discussion, but it was never answered
>to my satisfaction...  I have a PIC based card here that doesn't go
>absolutely to 0 VDC when power is off... the PIC always screws up...  Can
>someone PLEASE suggest a simple-reliable solution?  Can microchip put a
>GND-shorting switch in their parts?

You could use a reset device by Maxim to force the CPU to stay in a
reset state if the applied voltage is low. That would be the most reliable
solution - I think there are some very small surface mount devices that
can do this. This will also ensure that the next power up reset is clean.

Is the PIC device you are using specified to operate at lower voltages, if
so then detect this with a spare I/O pin and make it do nothing etc.

Its not practical to change a device design and a GND short could cause all
sorts of problems.

Have you tried something as simple as a pulldown resistor on your PIC voltage
pin ? You might not need a small value if the voltage is close to that at
which the device will not run at all.

Just how much current is there anyway to allow your PIC to operate when
the power is off ?

Rgds

Mike
Perth, Western Australia

Some say there is no magic but, all things begin with thought then it becomes
academic, then some poor slob works out a practical way to implement all that
theory, this is called Engineering - for most people another form of magic.
                                                                      Massen

1997\03\10@142714 by Shawn Ellis

flavicon
face
Well, I HAVE a load-resistor between +5V and GND (10K Ohm)  But it's kind
of slow to power all the way down still!  I'm afraid to go to a lower value
because everything runs through a +5VDC regulator (MAX is probably .5A).
If I do the Maxim thing, do you think that should be the end of it?  I
don't like the idea of my power not dropping to 0 even if my processor
resets!

>
> You could use a reset device by Maxim to force the CPU to stay in a
> reset state if the applied voltage is low. That would be the most
reliable
> solution - I think there are some very small surface mount devices that
> can do this. This will also ensure that the next power up reset is clean.
>
> Is the PIC device you are using specified to operate at lower voltages,
if
> so then detect this with a spare I/O pin and make it do nothing etc.
>
> Its not practical to change a device design and a GND short could cause
all
> sorts of problems.
>
> Have you tried something as simple as a pulldown resistor on your PIC
voltage
{Quote hidden}

becomes
> academic, then some poor slob works out a practical way to implement all
that
> theory, this is called Engineering - for most people another form of
magic.
>
Massen

1997\03\10@145002 by Mike

flavicon
face
At 02:22 PM 10/03/97 -0500, you wrote:
>Well, I HAVE a load-resistor between +5V and GND (10K Ohm)  But it's kind
>of slow to power all the way down still!  I'm afraid to go to a lower value
>because everything runs through a +5VDC regulator (MAX is probably .5A).
>If I do the Maxim thing, do you think that should be the end of it?  I
>don't like the idea of my power not dropping to 0 even if my processor
>resets!

The Maxim devices and those of other manufacturers will clamp the reset line
either high or low depending on the variety of the device. Most of them (I
think)
are clamping reset low, when power is up again to acceptable operating levels,
then the clamp is released. SO even if a couple of volts are on the device it
should not run - if the reset device is doing the right thing, then you can
forget
it, unless it is draining a battery and you want to minimise loss.

And yes - I think it should be the end of it but, and a big but, make sure you
try to minimise the effect of any other power source you do not want. If I
remember correctly from a much earlier post from you - you mentioned that there
was nothing you could do to stop power leaking into the PIC circuit from a
sensor
or transducer. I recommened you have another look at that.

Incidentally if you have a current meter, measure the current between a 1K
resistor to Vcc from ground, when the power is off. Your 10K is a bit big,
1K is only 5mA and is OK. If its going to be battery powered then remove the
pull down resistor(s) and go with the Maxim type devices.

Can you send me a .GIF or Protel schematic which shows where this extra power
is coming from AND getting coupled back into the PIC ? Or how about an ASCII
representative schematic ?

Rgds

Mike
Perth, Western Australia

There is no a'priori reason that the ultimate truth will be interesting
or even useful, those moments of frustration during philosophical debate
would be replaced by the sheer terror which accompanies true knowledge.

1997\03\10@151438 by Shawn Ellis

flavicon
face
Well, The schematic is in Autocad DWG and its kind of ad-hoc, so I hesitate
to tarnish my rep by sending this nasty thing out...  but if you can deal
with DWG or DXF I'll be glad to Email it to ya!  Yeah, that sensor problem
was a different system which I plan to optically isolate, this system is
interfaced to a device which holds the I/O line high via a separate power
supply (in the PC)  and that always puts a few extra millivolts on my
power-off.  Should I perhaps use a diode/relay/analog switch to turn off
the I/O when power is off?  I hope the optical isolation helps with the
other problem... mabye thats what I could do here as well.... But I DO need
something extra, because even with everything unplugged, the system STILL
holds enough voltage in the filter caps to screw it up even over-night!

>
> Can you send me a .GIF or Protel schematic which shows where this extra
power
> is coming from AND getting coupled back into the PIC ? Or how about an
ASCII
> representative schematic ?
>
> Rgds
>
> Mike
> Perth, Western Australia
>
> There is no a'priori reason that the ultimate truth will be interesting
> or even useful, those moments of frustration during philosophical debate
> would be replaced by the sheer terror which accompanies true knowledge.

1997\03\10@154655 by Mike

flavicon
face
At 03:11 PM 10/03/97 -0500, you wrote:
>Well, The schematic is in Autocad DWG and its kind of ad-hoc, so I hesitate
>to tarnish my rep by sending this nasty thing out...  but if you can deal
>with DWG or DXF I'll be glad to Email it to ya!  Yeah, that sensor problem
>was a different system which I plan to optically isolate, this system is
>interfaced to a device which holds the I/O line high via a separate power
>supply (in the PC)  and that always puts a few extra millivolts on my
>power-off.  Should I perhaps use a diode/relay/analog switch to turn off
>the I/O when power is off?  I hope the optical isolation helps with the
>other problem... mabye thats what I could do here as well.... But I DO need
>something extra, because even with everything unplugged, the system STILL
>holds enough voltage in the filter caps to screw it up even over-night!

Sorry can't read .DWG or .DXF files any longer - I deleted AutoSketch...

I think if you go for the reset clamping device it should be OK, you get the
extra benefit of a cleaner power up reset anyway. So the extra stuff with
relays, diodes etc should not be necessary.

The other thing which might help is put a series resistor on that IO line
from the PC - high enough so there's little power from it but not too high
so it will upset operation. If you are driving a CMOS input from this IO
line then somehwere around 100K should be fine. Go down in division by
2 each time if 100K is too high in practice.

Did you measure the current through a 1K resistor between Vcc and Gnd after
the power was off ? How big are those filter caps anyway ?

What happens if you replace the 10K with a 1K mentioned earlier ?

What is the operating voltage on your filter caps when the system is ON ?

Rgds

Mike

Social Scientist - "A person who thinks that a statistical
correlation is proof of cause and effect"

1997\03\10@155820 by Andy Kunz

flavicon
face
At 02:22 PM 3/10/97 -0500, you wrote:
>Well, I HAVE a load-resistor between +5V and GND (10K Ohm)  But it's kind
>of slow to power all the way down still!  I'm afraid to go to a lower value
>because everything runs through a +5VDC regulator (MAX is probably .5A).
>If I do the Maxim thing, do you think that should be the end of it?  I
>don't like the idea of my power not dropping to 0 even if my processor
>resets!

This is a typical PIC problem, esp the older (non-brownout) chips.

I like the Maxim SMT part.  TOKO and Panasonic have equivalent items I use
for prototyping in thru-hole.

Andy

==================================================================
Andy Kunz - Montana Design - 409 S 6th St - Phillipsburg, NJ 08865
         Hardware & Software for Industry & R/C Hobbies
       "Go fast, turn right, and keep the wet side down!"
==================================================================

1997\03\10@161330 by David W. Duley

picon face
In a message dated 97-03-10 13:55:07 EST, you write:

<<
Hey, all, I know this was already a discussion, but it was never answered
to my satisfaction...  I have a PIC based card here that doesn't go
absolutely to 0 VDC when power is off... the PIC always screws up...  Can
someone PLEASE suggest a simple-reliable solution?  Can microchip put a
GND-shorting switch in their parts?

 >>
why does'nt the VCC drop to zero?  Are there large caps, batteries?????
Need to know more.  I built a circuit that had a problem powering up.  If VCC
rises to working voltage too slowly then, yes, the PIC can screw up.  There
is a simple fix in the data books (at least for the PIC1684).
What voltage does the circuit drop to when off??  Could a couple of diode
drops in series with the VCC supplying the PIC do the trick??
Tell me more

Dave Duley
V.P. DreiTek Inc

1997\03\10@161334 by David W. Duley

picon face
In a message dated 97-03-10 15:32:16 EST, you write:

<<
Well, The schematic is in Autocad DWG and its kind of ad-hoc, so I hesitate
to tarnish my rep by sending this nasty thing out...  but if you can deal
with DWG or DXF I'll be glad to Email it to ya!  Yeah, that sensor problem
was a different system which I plan to optically isolate, this system is
interfaced to a device which holds the I/O line high via a separate power
supply (in the PC)  and that always puts a few extra millivolts on my
power-off.  Should I perhaps use a diode/relay/analog switch to turn off
the I/O when power is off?  I hope the optical isolation helps with the
other problem... mabye thats what I could do here as well.... But I DO need
something extra, because even with everything unplugged, the system STILL
holds enough voltage in the filter caps to screw it up even over-night!
 >>

I really don't think that your problem is the filter caps.   I think the
problem is that your VCC is coming up too slowly when you turn the system
back on.  This is a known problem with the pics.  Check the data book.  Mine
has a section warning about this and a solution is provided as well! How big
are the caps?  If you have very large filter caps like in a computer grade
linear supply (10000 uf plus) it will take a realtivly long period of time
for those caps to charge when the system is turned on.

Dave Duley
V.P. DreiTek Inc.

1997\03\10@211456 by Dwayne Reid

flavicon
face
>Hey, all, I know this was already a discussion, but it was never answered
>to my satisfaction...  I have a PIC based card here that doesn't go
>absolutely to 0 VDC when power is off... the PIC always screws up...  Can
>someone PLEASE suggest a simple-reliable solution?  Can microchip put a
>GND-shorting switch in their parts?
>

Shawn - I would look at a couple of things.  First: see if this is just a
matter of your filters holding charge.  Hook a scope between VCC & GND, then
touch a 100 ohm resistor from VCC to GND (with power off) and see what
happens.  If the supply nose-dives then recovers fairly slowly when you take
the resistor off, that is  most likely your problem.  If the supply recovers
very quickly, look to see if you have a signal coming in on one of the PIC
pins.

A quick and simple solution to the filter charge problem: connect a J175
JFET as follows:  S to Gnd, D to Vcc (+5v), G to 100K resistor, other side
of 100K resistor to unreg V+ (input of voltage regulator).  What this does
is monitor the UNREGULATED supply, when it drops below about 10 Vdc, the FET
conducts and looks like a 120 ohm resistor load on the 5v supply.  As soon
as the unregulated supply climbs above 10Vdc or so, the FET turns off and
looks like a very high resistance.

One other thing: how large are your filter caps?  If they are very large,
you may also have a problem with the 5V supply RISE time (must be less than
50 mSec from 0.5Vdc to 4.5 Vdc).

Dwayne Reid   <spam_OUTdwaynerTakeThisOuTspamplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, Alberta, CANADA
(403) 489-3199 voice     (403) 487-6397 fax

1997\03\10@231720 by Tony Matthews

flavicon
face
Shawn Ellis wrote:
{Quote hidden}

there is allways a better way as reading this list makes clear.May I
also have a copy of the dwg. .....tonyKILLspamspam@spam@magicnet.net

1997\03\10@231730 by Tony Matthews

flavicon
face
Shawn Ellis wrote:
>
> Hey, all, I know this was already a discussion, but it was never answered
> to my satisfaction...  I have a PIC based card here that doesn't go
> absolutely to 0 VDC when power is off... the PIC always screws up...  Can
> someone PLEASE suggest a simple-reliable solution?  Can microchip put a
> GND-shorting switch in their parts?
if you can isolate the mclr pin use a three terminal voltage monitor

1997\03\11@071528 by Kalle Pihlajasaari

flavicon
face
Hi,

> Well, I HAVE a load-resistor between +5V and GND (10K Ohm)  But it's kind
> of slow to power all the way down still!  I'm afraid to go to a lower value
> because everything runs through a +5VDC regulator (MAX is probably .5A).
> If I do the Maxim thing, do you think that should be the end of it?  I
> don't like the idea of my power not dropping to 0 even if my processor
> resets!

Use smaller Caps and higher impedance input circuits.

Some of the internal periferals require Vcc to go to zero, reset
is not enough to clear some persistent latchup conditions in some
silicon versions, check the errata.

Cheers
--
Kalle Pihlajasaari   kallespamKILLspamip.co.za   http://www.ip.co.za/ip
Interface Products   P O Box 15775, DOORNFONTEIN, 2028, South Africa
+ 27 (11) 402-7750   Fax: 402-7751    http://www.ip.co.za/people/kalle

DonTronics, Silicon Studio and Wirz Electronics uP Product Dealer

1997\03\11@100307 by Shawn Ellis

flavicon
face
>
> I really don't think that your problem is the filter caps.   I think the
> problem is that your VCC is coming up too slowly when you turn the system
> back on.  This is a known problem with the pics.  Check the data book.
Mine
> has a section warning about this and a solution is provided as well! How
big
> are the caps?  If you have very large filter caps like in a computer
grade
> linear supply (10000 uf plus) it will take a realtivly long period of
time
> for those caps to charge when the system is turned on.
>
> Dave Duley
> V.P. DreiTek Inc.

Nope, if I unplug the offending cable and let the VDC drop to GND, then
power up, I got no problems.

1997\03\11@100309 by Shawn Ellis

flavicon
face
> Did you measure the current through a 1K resistor between Vcc and Gnd
after
> the power was off ? How big are those filter caps anyway ?
>

47 uf & .1 uf, standard filter caps.

> What happens if you replace the 10K with a 1K mentioned earlier ?
>
It clamps it faster, but it still doesn't cut it.  One of these outputs is
still keeping VDC at .3!

> What is the operating voltage on your filter caps when the system is ON ?
>
4.92 VDC

1997\03\11@100311 by Shawn Ellis

flavicon
face
>   >>
> why does'nt the VCC drop to zero?  Are there large caps, batteries?????
> Need to know more.  I built a circuit that had a problem powering up.  If
VCC
> rises to working voltage too slowly then, yes, the PIC can screw up.
There
> is a simple fix in the data books (at least for the PIC1684).
> What voltage does the circuit drop to when off??  Could a couple of diode
> drops in series with the VCC supplying the PIC do the trick??
> Tell me more
>
Yeah, a couple of 47uf filter caps.

1997\03\11@100313 by Shawn Ellis

flavicon
face
>
> One other thing: how large are your filter caps?  If they are very large,
> you may also have a problem with the 5V supply RISE time (must be less
than
> 50 mSec from 0.5Vdc to 4.5 Vdc).
>
No, no problem with the rise time, if the volts go to 0, the circuit powers
up fine...

1997\03\11@123341 by Mike

flavicon
face
At 09:45 AM 11/03/97 -0500, you wrote:
>> Did you measure the current through a 1K resistor between Vcc and Gnd
>after
>> the power was off ? How big are those filter caps anyway ?
>
>47 uf & .1 uf, standard filter caps.

Thats OK - as long as the 47uF is on the INPUT of the regulator.

>> What happens if you replace the 10K with a 1K mentioned earlier ?
>>
>It clamps it faster, but it still doesn't cut it.  One of these outputs is
>still keeping VDC at .3!

O.3volts is nothing to be worried about at all ! - This might even be (self)
electrolysis of the filter caps - hehe... Or misreading of your meter, if
digital then probably an offset error or rectification of power supply hum
in the air. I had a circuit on my bench once which 'travelled' up to 22volts
on a set of high quality polystyrenes. Dare I say it the static bench lost
its resistor to ground and the overhead fluoro was VERY leaky. Putting the
static bench ground resistor back and fixing the fluoro still left 1.2v on
the circuit - which went away pretty quick when I measure it with a CRO, so
there wasn't much power there to do anything.

An earlier reply suggested the rise time was important and I agree, thats
another reason to use a reset chip - there are some 3 terminal surface mount
devices by Maxim and others - this will solve the power up/down but won't
give you peace of mind about those extra - electrons, by the way they are
everywhere just waiting to accumulate and get us in static zaps as well as
floating voltages on electrolytic caps. I just pulled  an old dead one out of
the junk box - and it has 0.08volts on it.

Incidentally to make a lightning/gravity detector get a very large (new)
wet electro, put it in a faraday cage (FC) and measure the voltage -  there
will be some correlation bewteen lightning activity AND position of moon !!
Naturally you'll have to amplify it with a very low noise screened amp, leave
as much in the FC as possible.

>> What is the operating voltage on your filter caps when the system is ON ?
>>
>4.92 VDC

I take it they are on the output of your 5v regulator, best to put them on the
input and make sure the max value of any single electro on the output of the
regulator is  not more than 10uF, I've found this best for stability. By using
0.1uF bypass and 1uF electro on output of reg is usually sufficient. Then, any
electro leakage on the input of the regulator is reduced before it gets to
the PIC. But really anything less than 1v is not to be worried about...

Large electros as bypass caps can cause more ringing since electros have a
bit more inductance than good polyesters or ceramics.

In conclusion:

1.      Filter caps on input of reg. and 1uF on reg output plus 0.1uF bypass(es)
2.      Keep 1K or similar on input of reg if you are worried
3.      Use reset chip

Rgds

Mike



Some say there is no magic but, all things begin with thought then it becomes
academic, then some poor slob works out a practical way to implement all that
theory, this is called Engineering - for most people another form of magic.
                                                                      Massen

1997\03\11@135102 by Andy Kunz

flavicon
face
At 09:45 AM 3/11/97 -0500, you wrote:
>> Did you measure the current through a 1K resistor between Vcc and Gnd
>after
>> the power was off ? How big are those filter caps anyway ?
>>
>
>47 uf & .1 uf, standard filter caps.
>
>> What happens if you replace the 10K with a 1K mentioned earlier ?
>>
>It clamps it faster, but it still doesn't cut it.  One of these outputs is
>still keeping VDC at .3!
>
>> What is the operating voltage on your filter caps when the system is ON ?
>>
>4.92 VDC


Shawn,

Now you know why Microchip added the brownout module to later chips.

Andy

==================================================================
Andy Kunz - Montana Design - 409 S 6th St - Phillipsburg, NJ 08865
         Hardware & Software for Industry & R/C Hobbies
       "Go fast, turn right, and keep the wet side down!"
==================================================================

1997\03\13@073709 by Larry G. Nelson Sr.

flavicon
face
At 03:11 PM 3/10/97 -0500, Shawn Ellis wrote:
{Quote hidden}

Did you try a diode from the VCC to the MCLR line? This way if the VCC drops
the chip is forced to reset. Normally you pull this line up thru a resistor
but putting a diode in parallel with the resistor will cause the loss of VCC
to pull the reset low much faster than it will go up.
Larry
Larry G. Nelson Sr.
.....L.NelsonKILLspamspam.....ieee.org
http://www.ultranet.com/~nr


'Power OFF'
1997\09\18@201221 by WF AUTOMA‚̀O
flavicon
face
Hello Pic Maniacs

       Does someone have a suggestion how may i do the Software for
PIC16F84, that when the power off, i had time to record in EEPROM DATA: 4
very important Data?

       Maw

------------------------------------------------------------------------*Check
http://www.inf.ufsc.br/~jbosco/labvir.htm and do remote experiments with
microcontrollers!

1997\09\19@012848 by Mike Keitz

picon face
On Thu, 18 Sep 1997 21:19:31 -0700 WF AUTOMA=?iso-8859-1?Q?=C7=C3O ?=
<EraseMEwfspam_OUTspamTakeThisOuTAMBIENTE.COM.BR> writes:
>Hello Pic Maniacs
>
>        Does someone have a suggestion how may i do the Software for
>PIC16F84, that when the power off, i had time to record in EEPROM
>DATA: 4
>very important Data?

This is more a hardware question than a software one.  To ensure "time to
record," the hardware needs to give the PIC adequate warning that the
power is about to go off.  Upon receiving the warning, the PIC starts
writing the important data to EEPROM.  After the writing is done the PIC
should try to stop as fully as possible so when the power goes off it is
unlikely to write something else into EEPROM by mistake.

The warning required is on the order of 10 ms per byte to be stored.
Often this is done by sensing the input voltage to the voltage regulator.
For example, if the PIC runs from a 5V supply derived by regulating a
12V supply down, the nominal 12V input would be compared to say 8 or 9 V.
When the voltage reaches this level the PIC concludes that the 12V power
has been removed, thus the 5V is about to fail.  The regulator needs a
capacitor on its input sufficient to hold up the PIC supply voltage while
the writing is in progress.  The size of the capacitor is readily
calculated C = I * t / V.  For example if the PIC and regulator use 10
mA, the save will take 50 ms, and the capacitor voltage can drop by 3V
during the save, the minimum required capacitor value is 166 uF.

The voltage drop warning could cause an interrupt or it could just be
polled, since a delay of a few ms in recognizing it is not a problem.

For cases where it would be difficult for the hardware to provide advance
warning that power is failing, it is necessary to maintain a constant
"shadow" of the important data in the EEPROM.  The algorithm to do this
takes into account how often the important data changes, how often the
power is to fail, and the EEPROM's rated life.  If the important data
changes only once each hour, it could be saved to EEPROM everytime it
changes (10 years = 87,600 hours).  If it changes more rapidly than this
then the saving must be done less often to keep from wearing the EEPROM
out.  Not saving every change of course makes it likely that an old
version will be recalled when the power comes back on.

Another problem with periodic saving is that if power fails during a save
the data may be garbled.  One solution to this would be to save two
copies with a scheme such as CRC applied to each copy to check if it is
valid.  If upon turning the power back on, a copy fails the CRC the other
one would be used.  The bad copy would be fixed by rewriting it from the
good one.  (If both copies fail CRC, obviously this is a problem.  This
shouldn't happen if it is just power on/off causing garbled data to be
written)

1997\09\19@071645 by STEENKAMP [M.ING E&E]

flavicon
picon face
Hi,

> Another problem with periodic saving is that if power fails during a save
> the data may be garbled.  One solution to this would be to save two
> copies with a scheme such as CRC applied to each copy to check if it is
> valid.  If upon turning the power back on, a copy fails the CRC the other
> one would be used.  The bad copy would be fixed by rewriting it from the
> good one.  (If both copies fail CRC, obviously this is a problem.  This
> shouldn't happen if it is just power on/off causing garbled data to be
> written)

A method I have used keeps two copies of the data and a pointer byte.
I write alternately to the one or the other.  I first write the data and
then write the single pointer byte to indicate which of the entries
contain the most recent info.  This method makes sure that the data you
read is always valid (although it might not be the newest data).

Niki

1997\09\19@093022 by WF AUTOMA‚̀O

flavicon
face
Mike Keitz wrote:
{Quote hidden}

i WILL TRY ALL THE POSSIBILITIES THAT YOU OFFERED ME! OTHER OPTION THAT I WILL
TRY IS TO VERIFY
THE 60HZ OF POWER (Circuit Connected at PORTB (interrupt on change)). EACH
+-32ms i will verify
IF THERE WAS A CHANGE, LOOKING THE FLAG INTERRUPT ON CHANGE. HUMM, I DON'T KNOW
IF 32ms IT'S TOO
MUCH TIME TO WAIT, BETWEEN VERIFY!
THANK YOU VERY MUCH FOR THESE INFORMATIONS!

MIGUEL.

1997\09\19@202252 by WF AUTOMA‚̀O

flavicon
face
N STEENKAMP [M.ING E&E] wrote:
{Quote hidden}

I resolved my problem with 1000uf Capacitor on Power of PIC16f84! And a circuit
that verify if
the power off. When this happen, i have disponible time to record my information
with garanty, i
think!
I put jumper, for the user configurate for a new sequence of Disponible address,
for example:

JUMPER       POSITIONS
0 0 0        0,1,2
0 0 1        2,3,4
0 1 0        5,6,7
.               .
.               .
.               .

Mig.

1997\09\22@085056 by Mike Watson

flavicon
picon face
In message  <@spam@1BD1B35E65KILLspamspamfirga.sun.ac.za> KILLspamPICLISTKILLspamspamMITVMA.MIT.EDU writes:
> Hi,
>
> > Another problem with periodic saving is that if power fails during a save
> > the data may be garbled.  One solution to this would be to save two
> > copies with a scheme such as CRC applied to each copy to check if it is
> > valid.  If upon turning the power back on, a copy fails the CRC the other
> > one would be used.  The bad copy would be fixed by rewriting it from the
> > good one.  (If both copies fail CRC, obviously this is a problem.  This
> > shouldn't happen if it is just power on/off causing garbled data to be
> > written)
>
> A method I have used keeps two copies of the data and a pointer byte.
> I write alternately to the one or the other.  I first write the data and
> then write the single pointer byte to indicate which of the entries
> contain the most recent info.  This method makes sure that the data you
> read is always valid (although it might not be the newest data).
>
Niki,

Is there not a danger with this method that the pointer location
could get corrupted if it is being written at the same time that
the power is being removed?

Have you a mechanism to deal with that?


Best regards,

Mike Watson

1997\09\22@110742 by John Payson

picon face
> > A method I have used keeps two copies of the data and a pointer byte.
> > I write alternately to the one or the other.  I first write the data and
> > then write the single pointer byte to indicate which of the entries
> > contain the most recent info.  This method makes sure that the data you
> > read is always valid (although it might not be the newest data).
>
> Is there not a danger with this method that the pointer location
> could get corrupted if it is being written at the same time that
> the power is being removed?

Well, if you only look at one bit of the pointer this shouldn't pose a
problem.  Since the pointer byte will only [usually] be written when both
copies of the data are valid, it won't matter what value is read for the
pointer in those cases.

Even the annoying odd cases (e.g. one copy of the data is corrupt when the
system starts up) can be dealt with safely if the data is written to the
corrupt page (fixing it) before the pointer is written for the first time.

1997\09\22@165903 by Mike Keitz

picon face
On Mon, 22 Sep 1997 13:24:04 GMT Mike Watson <RemoveMEmikeTakeThisOuTspamD-M-G.DEMON.CO.UK>
writes:

>>
>> A method I have used keeps two copies of the data and a pointer
>byte.
>> I write alternately to the one or the other.  I first write the data
>and
>> then write the single pointer byte to indicate which of the entries
>> contain the most recent info.  This method makes sure that the data
>you
>> read is always valid (although it might not be the newest data).

>Is there not a danger with this method that the pointer location
>could get corrupted if it is being written at the same time that
>the power is being removed?
>
>Have you a mechanism to deal with that?

It is important that the new pointer is written *after* the data.  If
power fails while writing to the new data block, the pointer will still
point to the old one, so the incompletely written data will not be used.
If the new data block is written but the power fails while writing the
pointer, both blocks of data will be valid (one old, one new).  The read
routine must mask the pointer so it always reads one or the other data
block.  If the pointer is bad the worst that could happen is the older
data will be retreived, the same result as if the new data were not
completely written.

All this is based on the assumption that cutting the power off in the
middle of an EEPROM write will only affect the byte being written.

1997\09\23@035832 by Mike Watson

flavicon
picon face
In message  <spamBeGone19970922.144517.6878.3.mkeitzspamBeGonespamjuno.com> TakeThisOuTPICLISTEraseMEspamspam_OUTMITVMA.MIT.EDU
writes:
{Quote hidden}

Is this a good assumption to make? Does it hold good with the
on board C84 EEProm as well as external IIC EEProm and FRAM?

This has more than academic interest for me as I am inheriting a
project which exhibits ee-memory loss.


Cheers,

Mike Watson



--
Mayes uk

1997\09\23@062757 by mikesmith_ozNOSP*M

flavicon
face
On 23 Sep 97 at 8:51, Mike Watson wrote:

<snip>

> Is this a good assumption to make? Does it hold good with the
> on board C84 EEProm as well as external IIC EEProm and FRAM?
>
> This has more than academic interest for me as I am inheriting a
> project which exhibits ee-memory loss.

Are you getting NV loss with FRAM's? With their fast write cycle?
MikeS
<mikesmith_ozNOSP*M.relaymail.net>
(remove the you know what before replying)

1997\09\23@065707 by : Cassie Carstens

flavicon
face
{Quote hidden}

Hi
Like somebody said; *my penny's worth*
I also had some values to save to EEPROM in a 16c84 in case of power
loss. I fitted a BIG capacitor over the supply line. Then I placed a
diode in the positive line on the supply side of the cap. Before that
was a potential divider and a Zener for protection. The output of
this devider went to a input portpin to cause a interupt. After
first setting all drive ports to input, there was ample time to store
to eeprom. The rest of the remaining time was spend reading the
supply-fail pin.

Regards
CC

1997\09\23@120606 by Mike Watson

flavicon
picon face
In message  <RemoveME199709231017.TAA17977spam_OUTspamKILLspampasteur.dialix.com.au>> mikesmith_ozNOSP*RemoveMEMTakeThisOuTspamspamrelaymail.net writes:
> On 23 Sep 97 at 8:51, Mike Watson wrote:
>
> <snip>
>
> > Is this a good assumption to make? Does it hold good with the
> > on board C84 EEProm as well as external IIC EEProm and FRAM?
> >
> > This has more than academic interest for me as I am inheriting a
> > project which exhibits ee-memory loss.
>
> Are you getting NV loss with FRAM's? With their fast write cycle?

I haven't tried it yet - it will be the first thing I try when
I get hold of the hardware.

I think I will still implement the double buffer scheme if the FRAM
cures the problem just to be on the safe side.

Regards,

Mike Watson

More... (looser matching)
- Last day of these posts
- In 1997 , 1998 only
- Today
- New search...