'input clamp vs output current'
I have a circuit in which I use the PIC IO pins to clamp a
voltage at the pin to VDD at very low current. The current
into the pin is about 3uA. I've used two methods and find a
difference in operation that I can't explain. The pins are
RA0,RA1 on a 16C622 and the pins are configured as "digital"
(comparator is disabled). VDD is 3.0V. See the below
13VDC >-----/\/\/\-----|RA0 (input or output high)
Method 1. Drive the pin as an output high. 3uA current flows
into the pin to VDD through the P channel FET (FET conducts in
Method 2. Set the pin as an input. 3uA current flows into the
pin to VDD through the protection diode.
My measurements show that the pin sits at about VDD with #1,
and .4V above VDD with #2.
I drive two pins each with about 3uA current. The total
quiescent current is 6uA higher using method #2, why?
(Note: 6uA is 20% of my total current, so it does matter).
More on my problem with increasing supply current when
protection diodes are forward biased. My circuit forward
biases the upper protection diode with a very small current.
I did some measurements and found that supply current increases
in proportion to input protection diode forward bias current.
With zero current into the protection diode my PIC draws
30.5uA. With 2.5uA into each of two pins, total current
increases to 34.1uA (the sum of the pin currents plus supply
current). With 5uA into each of two pins, total current
increases to 37.6uA.
The same circuit with the same pins driven as high outputs
results in no increase in total current when current into the
pins varies from 0 to 5uA each.
My conclusion is when designing micropower circuits avoid
forward biasing the upper input protection diodes.
Anyone seen similar results?
On Thu, 29 Jul 1999, Jim Hartmann wrote:
Could this be the onset of a latchup condition? I realize that currents
induced by latch up are catastrophic, but perhaps there's a similar
phenomenon taking place. The P-N junction of the input protection diode
may in fact be part of a parasitic transistor. By forward biasing this
junction, you may inadvertantly cause parasitic currents to flow else
where. This is only a plausible explanation - I have no experience with
|Jim, just a question:
Do you have a way to scope this supply current when biasing diodes
forward? Is it a steady DC current?
Some input circuits use shadow gates inside that mirror the input
voltage/current to the actual internal circuit. This is done to protect
and isolate things. Sometimes when you input some current, it is
reflected to the internal gates, generating a mirrored current consume.
If it is the case, when you program the pin port for output, this
mirroring does not happens, what does not cause the increase in supply
If the input current is caused by a voltage above the chip VDD, as you
said, remember that the input protective diodes in real are not "diodes"
but silicon junctions to do the job. Some chips use a technique to keep
the VDD steady when an overvoltage enters a pin, they increase the
supply current in a proportional way. This is done to make sure the
protection does not interfere into the other parts of the chip,
otherwise the deviated current to VDD would be poured all over the other
parts of the chip. If the protection would be just a diode connecting
the pin to VDD, and if you apply 6 Volts to that pin, your VDD "would"
increase to 5.4 Volts, or 6 minus the internal diode voltage drop,
right?, it means all the chip would be supplied with 5.4V... it could be
I have a circuit that works from 3.8 to 5.2Vdc, some tests were done to
try to feed some extra micro or milliamps to the VDD via an input pin,
connected to another machine that supply its data lines with steady TTL
5V or zeroV. The idea was to "steal" this small current back into my
circuit VDD, when its battery was low. Primarily we used Schoktty
diodes from the data lines to VDD, then we thought why not allow the
protective input diodes (inside of the chip) to do this job... wrong
action. What happened was just as you described. When the input pin
received the external 5Vdc data line, and the local VDD was 4Vdc, the
local circuit sucked more current from the weak battery instead to
relief it by using the input data line deviated current.... it took a
while to understand why...
Jim Hartmann wrote:
|On Thu, 29 Jul 1999 17:35:58 -0600 Jim Hartmann
<SILENTKNIGHT.COM> writes: Jim_Hartmann
> I did some measurements and found that supply current increases
> in proportion to input protection diode forward bias current.
It sounds like you are starting to turn on the parasitic transistor which
caused the dreaded "SCR latchup" in early CMOS devices. New devices are
designed not to latch up destructively but that doesn't mean that no
current flows at all.
> The same circuit with the same pins driven as high outputs
> results in no increase in total current when current into the
> pins varies from 0 to 5uA each.
What you may be able to do to reduce the supply current is make the pin
an output most of the time and drive it to the last read input state.
This keeps the protection diode from conducting. Only change it to an
input briefly to read new states. When the pin was high and it goes low
though, a relatively large current will flow from Vdd out of the high
output through the current limiting resistor until the pin is read again.
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